M65827FP Datasheet, PDF (43/52 Pages) Mitsubishi Electric Semiconductor – 10-TIMES SPEED CD-DSP

8.Digital audio interface output
The digital audio interface signal according to EIAJ regulation CP-1201 "digital audio interface" is
output to the DOTX pin.
Validity flag is set automatically to "1" when the interpolated word is transmitted. The data that is read
from the subcode interface block is transmitted to user data. Channel status clock accuracy and source
number can be set using the MCU interface.
Audio Data
Shift Register
16
Shift Register
Preamble Generator
Bi-phase
Mark Modulation
DOTX
Source No.
Clock Accuracy
(MCU I/F)
Channel
Status
Register
CUV
Parity
Generator
EST
Shift Register
Timing
Generator
7
SBCQ~W
Fig. 7: Digital out block diagram
B: L-channel, the head of blocks
M: L-channel, not the head of blocks
W: R-channel
SYNC
AUX Extended bit
Audio DATA
Parity bit
Channel status
User data
Validity flag
V UCP
4 bit
4 bit
4 bit
"0"
LSB
16 bit
Sub frame format
MSB 1 1 1 1
Subframe
Subframe
M L-channel W R-channel
B L-channel
W R-channel
M L-channel
Frame 191
Frame 0
Frame format
Frame 1
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