MH32S72VJA-6 Datasheet, PDF (42/56 Pages) Mitsubishi Electric Semiconductor – 2,415,919,104-BIT ( 33,554,432-WORD BY 72-BIT ) Synchronous DYNAMIC RAM

CLK
/CS
/RAS
/CAS
MITSUBISHI LSIs
MH32S72VJA-6
2,415,919,104-BIT ( 33,554,432-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Read Interrupted by Precharge
BL=4,CL=4 Latch mode(REGE="H")
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
tRRD
tRCD
tRP
tRCD
/WE
CKE
DQM
DQM read latency=3
A0-9
X
XY
Y
X
Y
A10
X
X
X
A11
X
X
X
BA0,1
0
10
1 01
1
1
DQ
REGE
Q0 Q0 Q0 Q0 Q1 Q1
ACT#0
READ#0
ACT#1
PRE#0
READ#1
PRE#1
ACT#1
READ#1
Burst Read is not interrupted
by Precharge of the other bank.
Burst Read is interrupted
by Precharge of the same bank.
Italic parameter indicates minimum case
MIT-DS-0311-0.0
MITSUBISHI
ELECTRIC
8/May. /1999
42