MH64D72KLH-75 Datasheet, PDF (4/39 Pages) Mitsubishi Electric Semiconductor – 4,831,838,208-BIT (67,108,864-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module

Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH64D72KLH-75,-10
4,831,838,208-BIT (67,108,864-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module
PIN FUNCTION
SYMBOL
TYPE
CK0,/CK0
Input
CKE0, CKE1
Input
DESCRIPTION
Clock: CK0 and /CK0 are dif f erential clock inputs. All address and control input
signals are sampled on the crossing of the positive edge of CK0 and negativ e
edge of /CK0. Output (read) data is ref erenced to the crossings of CK0 and
/CK0 (both directions of c rossing).
Clock Enable: CKE0 controls SDRAM internal clock. When CKE0 is low, the
internal clock f or the f ollowing cy c le is ceased. CKE0 is also used to select
auto / self ref resh. After self ref resh mode is started, CKE0 becomes
asy nchronous input. Self ref resh is maintained as long as CKE0 is low.
/S0, /S1
Input
Phy s ical Bank Select: When /S0,/S1 is high, any command means No Operation.
/RAS, /CAS, /WE
Input
Combination of /RAS, /CAS, /WE defines basic commands.
A0-12
Input
A0-12 specif y the Row / Column Address in conjunction with BA0,1. The Row
Address is specif ied by A0-12. The Column Address is specif ied by A0-9.
A10 is also used to indicate precharge option. When A10 is high at a read / write
command, an auto precharge is perf ormed. When A10 is high at a precharge
command, all banks are precharged.
BA0,1
DQ 0-64
CB 0-7
DQS0-8
DM0-8
Input
Bank Address: BA0,1 specifies one of four banks in SDRAM to which a command is applied. BA0,1
must be set with ACT, PRE, READ, WRITE commands.
Input / Output Data Input/Output: Data bus
Input / Output ^{Data Strobe: Output with read data, input with write data. Edge-aligned with read}
data, centered in write data. Used to capture write data.
Input
Masks write data when high, issued concurrently with input data. Both DM and DQ have a write
latency of one clock once the write command is registered into the SDRAM.
Vdd, Vss
Power Supply Power Supply for the memory array and peripheral circuitry.
VddQ, VssQ
Vddspd
Vref
RESET
SDA
SCL
SA0-2
VDDID
Power Supply VddQ and VssQ are supplied to the Output Buffers only.
Power Supply Power Supply for SPD
Input
SSTL_2 reference voltage.
Input
This signal is asy nchronous and is driv en low to the register in order to
guarantee the register outputs are low.
Input / Output ^{This bidirectional pin is used to transf er data into or out of the SPD EEPROM.}
A resistor must be connected f rom the SDA bus line to VDD to act as a pullup.
Input
Input
This signal is used to clock data into and out of the SPD EEPROM. A resistor
may be connected f rom the SCL bus time to VDD to act as a pullup.
These signals are tied at the system planar to either VSS or VDD to conf igure
the serial SPD EEPROM address range.
VDD identif ication f lag
MIT-DS-0390-1.0
MITSUBISHI ELECTRIC
24.Nov.2000
4