MH32S72QJA-7 Datasheet, PDF (4/56 Pages) Mitsubishi Electric Semiconductor – 2415919104-BIT ( 33554432-WORD BY 72-BIT ) Synchronous DYNAMIC RAM

MITSUBISHI LSIs
MH32S72QJA-7, -8
2415919104-BIT ( 33554432-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
PIN FUNCTION
CK0
Input
CKE0
Input
Master Clock:All other inputs are referenced to the rising
edge of CK
Clock Enable:CKE controls internal clock.When CKE is
low,internal clock for the following cycle is ceased. CKE is
also used to select auto / self refresh. After self refresh
mode is started, CKE E becomes asynchronous input.Self
refresh is maintained as long as CKE is low.
/S0,2
Input
Chip Select: When /S is high,any command means
No Operation.
/RAS,/CAS,/W
Input ^{Combination of /RAS,/CAS,/W defines basic commands.}
A0-11
BA0-1
DQ0-63
CB0-7
DQM0-7
Vdd,Vs s
Input
Input
A0-11 specify the Row/Column Address in conjunction with
BA.The Row Address is specified by A0-11.The Column
Address is specified by A0-10.A10 is also used to indicate
precharge option.When A10 is high at a read / write
command, an auto precharge is performed. When A10 is
high at a precharge command, both banks are precharged.
Bank Address:BA0,1 is not simply BA.BA0,1 specifies
the bank to which a command is applied.BA must be set
with ACT,PRE,READ,WRITE commands
Input/Output ^{Data In and Data out are referenced to the rising edge}
of CK
Input
Din Mask/Output Disable:When DQMB is high in burst
write.Din for the current cycle is masked.When DQMB is
high in burst read,Dout is disabled at the next but one cycle.
Power Supply _{Power Supply for the memory mounted module.}
REGE
Output
Register enable:When REGE is low,All control signals and
address are buffered. (Buffer mode) When REGE is
high,All control and address are latched. (Latch mode)
MIT-DS-0330-0.0
MITSUBISHI
ELECTRIC
16/Jun/1999
4