MH64S72QJA-6 Datasheet, PDF (38/56 Pages) Mitsubishi Electric Semiconductor – 4,831,838,208-BIT ( 64,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM

CLK
/CS
/RAS
/CAS
MITSUBISHI LSIs
MH64S72QJA -6
4,831,838,208-BIT ( 64,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Read Interrupted by Read / Write
BL=4,Latch mode(REGE="H")
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
tRRD
tRCD
/WE
CKE
DQM
DQM read latency=3
A0-9
X
XY
YY
Y
Y
Y
A10
X
X
A11
X
X
BA0,1
0
DQ
REGE
10
00
1
0
Q0 Q0 Q0 Q0 Q0 Q0 Q1 Q1 Q0
0
D0
ACT#0
READ#0 READ#0 READ#0
READ#0
WRITE#0
ACT#1
READ#1
blank to prevent bus contention
Burst Read can be interrupted by Read or Write of any active bank.
MIT-DS-334-0.0
Italic parameter indicates minimum case
MITSUBISHI
ELECTRIC
17/Jun. /1999 ₃₈