MH28D72KLG-75 Datasheet, PDF (37/39 Pages) Mitsubishi Electric Semiconductor – 9,663,676,416-BIT (134,217,728-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module

Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH28D72KLG-75,-10
9,663,676,416-BIT (134,217,728-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module
EEPROM Components A.C. and D.C. Characteristics
Symbol
VCC
VSS
VIH
VIL
VOL
Parameter
Supply Voltage
Supply Voltage
Input High Voltage
Input Low Voltage
Output Low Voltage
Limits
Min. Typ.
2.2
0
0
Vccx0.7
-1
Max.
5.5
0
Vcc+0.5
Vccx0.3
0.4
Units
V
V
V
V
V
EEPROM A.C.Timing Parameters (Ta=0 to 70°C)
Symbol
Parameter
fSCL
TI
TAA
TBUF
SCL Clock Frequency
Noise Supression Time Constant at SCL, SDA inputs
SCL Low to SDA Data Out Valid
Time the Bus Must Be Free before a New
Transmission Can Start
THD:STA Start Condition Hold Time
TLOW
Clock Low Time
THIGH Clock High Time
TSU:STA Start Condition Setup Time
THD:DAT Data In Hold Time
TSU:DAT Data In Setup Time
TR
SDA and SCL Rise Time
TF
SDA and SCL Fall Time
TSU:STO Stop Condition Setup Time
TDH
Data Out Hold Time
TWR
Write Cycle Time
Limits
Min. Max.
100
200
3.5
4.7
4.0
4.7
4.0
4.7
0
250
1
300
4.0
100
10
Units
KHz
ns
us
us
us
us
us
us
us
ns
us
ns
us
ns
ms
tWR is the time from a valid stop condition of a write sequence to the end of the EEPROM internal erase/program cycle.
SCL
SDA
IN
TF
THIGH
TR
TLOW
TSU:STA
THD:STA
THD:DAT
TSU:DAT
TSU:STO
TAA
TDH
TBUF
SDA
OUT
MIT-DS-0412-0.1
MITSUBISHI ELECTRIC
21.Mar.2001
37