M37735MHBXXXFP Datasheet, PDF (35/90 Pages) Mitsubishi Electric Semiconductor – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

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MITSUBISHI MICROCOMPUTERS
M37735MHBXXXFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
The internal/external clock polarity is selected with bit 6 (CPL) of the
UARTj transmit/receive control register 0. When bit 6 is “0”, transmit
data is output at the CLKj’s falling edge in transmitting, received data
is input at the CLKk’s rising edge in receiving, and the CLKi level is
“H” not in transferring (transmitting/receiving). When bit 6 is “1”,
reversely, transmit data is output at the CLKj’s rising edge in
transmitting, received data is input at the CLKk’s falling edge in
receiving, and the CLKi level is “L” not in transferring. Bit transfer
order of transmit/received data, which is LSB first or MSB first (Note),
is selected with bit 7 (TFM) of the UARTj transmit/receive control
register 0. LSB first is selected when bit 7 is “0”, and MSB first is
selected when bit 7 is “1”. However, UART2’s function is fixed to the
function specified by TxS=CPL=TFM=“0”, and it cannot be changed.
Note that, only in the UART0 transmission mode, the transmission
clock can be output not only from the CLK0 pin but also from the
other output pins (CLKS0, CLKS1). Transmission clock output multiple-
selection mode is set with the serial transmit control register and
others. For details, refer to the section on transmission.
Note. When LSB first is selected, data is transmitted/received
beginning at the least significant bit (LSB). When MSB first is
selected, data is transmitted/received beginning at the most
significant bit (MSB).
Transmission
Transmission is started when the bit 0 (TEj flag) of the UARTj transmit/
receive control register 1 is “1”, bit 1 (TIj flag) of one is “0”, and the
CTSj input is “L”.
Transmit data is output each time when the transmission clock (CLKj)
level changes from “H” to “L” with bit 6 (CPL) of the UARTj transmit/
receive control register 0 “0” or is output each time when the CLKj
level changes from “L” to “H” with CPL “1”. For details, refer to Figure
42. In addition, transmit data is output beginning at the least significant
bit (LSB) with bit 7 (TFM) of the UARTj transmit/receive control register
“0” or is output beginning at the most significant bit (MSB) with TFM
“1”.
The TIj flag indicates whether the transmission buffer register is empty
or not. It is cleared to “0” when date is written in the transmission
buffer register and set to “1” when the contents of the transmission
buffer register is transferred to the transmission register.
Transmission
clock
TEj
1 / fi ! ( n + 1 ) ! 2
TIj
CTSj
(CPL =
“0” )
CLKj
(CPL =
“1” )
Write in transmission buffer register Transmission register Transmission buffer register
1 / fi ! ( n + 1 ) ! 2
Stopped because TEj = “0”
TENDj
(TFM =
“0” )
TXDj
(TFM =
“1” )
D0 D1 D2 D3 D4 D5 D6 D7
D0 D1 D2 D3 D4 D5 D6 D7
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
D0 D1 D2 D3 D4 D5 D6 D7
D7 D6 D5 D4 D3 D2 D1 D0
TXEPTYj
Fig. 42 Clock synchronous serial I/O timing
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