MH8S72PHC-7 Datasheet, PDF (33/55 Pages) Mitsubishi Electric Semiconductor – 603979776-BIT (8388608 - WORD BY 72-BIT)SynchronousDRAM

Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8S72PHC -7,-8,-10
603979776-BIT (8388608 - WORD BY 72-BIT)SynchronousDRAM
AC TIMING REQUIREMENTS (SDRAM Component)
(Ta=0 ~ 70°C, Vdd = 3.3 ± 0.3V, Vss = 0V, unless otherwise noted)
Input Pulse Levels:
0.8V to 2.0V
Input Timing Measurement Level: 1.4V
Symbol Parameter
Limits
-7
-8
-10
Unit
Min. Max. Min. Max. Min. Max.
tCLK _{CK cycle time}
CL=2 10
13
CL=3 ¹⁰
10
tCH
tCL
tT
tIS
tIH
tRC
tRCD
tRAS
tRP
tWR
tRRD
CK High pulse width
CK Low pilse width
Transition time of CK
Input Setup time(all inputs)
Input Hold time(all inputs)
Row cycle time
Row to Column Delay
Row Active time
Row Precharge time
Write Recovery time
Act to Act Deley time
3
3
3
3
1 10 1 10
2
2
1
1
70
70
20
20
50 100K 50 100K
20
20
20
20
20
20
tRSC Mode Register Set Cycle time 20
20
tSRX Self Refresh Exit time
10
10
tPDE Power Down Exit time
tREF Refresh Interval time
10
10
64
64
15
ns
10
ns
4
ns
4
ns
1 10 ns
3
ns
1
ns
90
ns
30
ns
60 100K ns
30
ns
15
ns
20
ns
20
ns
10
ns
10
ns
64 ms
CK
Signal
1.4V Any AC timing is
referenced to the input
1.4V ^{signal crossing through}
1.4V.
MIT-DS-0283-0.0
MITSUBISHI
ELECTRIC
( 33 / 55 )
9/ Dec. /1998