MH32D72AKLA-10 Datasheet, PDF (31/38 Pages) Mitsubishi Electric Semiconductor – 2,415,919,104-BIT (33,554,432-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module

Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH32D72AKLA-10,-75
2,415,919,104-BIT (33,554,432-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module
[Initialize and Mode Register sets]
/CLK
CLK
Command
NOP
PRE
EMRS
MRS
PRE
AR
A0-9,11,12
Code
Code
A10
BA0,1
DQS
1
Code
Code
1
10
00
DQ
AR
MRS
ACT
Code
Xa
Code
Xa
00
Xa
tMRD tMRD tRP
tRFC tRFC tMRD
[AUTO REFRESH]
Single cycle of auto-refresh is initiated with a REFA(/CS=/RAS=/CAS=L,/WE=CKE=H) command. The
refresh address is generated internally. 4096 REFA cycles within 64ms refresh 128M bits memory cells.
The auto-refresh is performed on 4 banks concurrently. Before performing an auto refresh, all banks must
be in the idle state. Auto-refresh to auto-refresh interval is minimum tRFC . Any command must not be
supplied to the device before tRFC from the REFA command.
/CLK
CLK
Auto-Refresh
/CS
/RAS
NOP or DESELECT
/CAS
/WE
CKE
A0-12
BA0,1
tRFC
Auto Refresh on All Banks
Auto Refresh on All Banks
MIT-DS-0398-1.1
MITSUBISHI ELECTRIC
24.Nov.2000
31