M5M4V4S40CTP-12 Datasheet, PDF (30/45 Pages) Mitsubishi Electric Semiconductor – 4M (2-BANK x 131072-WORD x 16-BIT) Synchronous DRAM

SDRAM (Rev. 0.3)
Feb ‘97 Preliminary
MITSUBISHI LSIs
M5M4V4S40CTP-12, -15
4M (2-BANK x 131072-WORD x 16-BIT) Synchronous DRAM
SWITCHING CHARACTERISTICS
(Ta=0 ~ 70°C, Vdd = VddQ = 3.3 ± 0.3v, Vss = VssQ = 0v, unless otherwise noted)
Limits
Symbol Parameter
-12
-15
Unit
Min. Max. Min. Max.
CL=1
27
30 ns
tAC Access time from CLK CL=2
9.5
12 ns
CL=3
8
9
ns
tCAC Column Access Time
24.5
30 ns
tRAC Row Access Time
54.5
60 ns
Output Hold time from
tOH _CLK
3
3
ns
Delay time, output low
tOLZ _{impedance from CLK}
0
0
ns
Delay time, output high
tOHZ _{impedance from CLK}
3
8
3
10 ns
Output Load Condition
VTT=1.4V
VOUT
50 ohm
VREF =1.4V
50pF
CLK
CLK
DQ
Output Timing Measurement
Reference Point
1.4V
DQ
tAC
tOH
tOHZ
MITSUBISHI ELECTRIC
1.4V
1.4V
1.4V
30