M16C62A Datasheet, PDF (270/274 Pages) Mitsubishi Electric Semiconductor – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Mitsubishi microcomputers
M16C / 62A Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Revision History
Version
Contents for change
REV.A1
Page 145 Note 2
• Before data can be written to the SI/Oi transmit/receive register (addresses
036016, 036416), the CLKi pin input must be in the low state. Also, before rewriting
the SI/Oi Control Register (addresses 036216, 036616)’s bit 7 (SOUTi initial value
set bit), make sure the CLKi pin input is held low. ---> • Before data can be written
to the SI/Oi transmit/receive register (addresses 036016, 036416), the CLKi pin
input must be in the high state. Also, before rewriting the SI/Oi Control Register
(addresses 036216, 036616)’s bit 7 (SOUTi initial value set bit), make sure the CLKi
pin input is held high.
Revision
date
99.12.21
REV. A2
Page 43, Figure 1.10.6
Note: Writing a value to an address after “1” is written to this bit returns the bit to
“0” . Other bits do not automatically return to “0” and they must therefore
be reset by the program.
00.7.3
Page 144, Figure 1.16.32, bit 5 of the SI/Oi control register (i=3, 4)
Transfer direction lect bit --->Transfer direction select bit
Page 144, Figure 1.16.32, Note 2
When using the port as an input/output port by setting the SI/Oi port select bit (i =
3, 4) to “1”, be sure to set the sync clock select bit to “1”.
--->
When using the port as an input/output port by setting the SI/Oi port select bit (i =
3, 4) to “0”, be sure to set the sync clock select bit to “1”.
Page 115, 139, Bit 3 of the UART2 special mode register 2 (bit symbol)
ASL --> ALS
REV. B
Page 2 Note is added in Figure 1.1.1.
Page 3 Note is added in Figure 1.1.2.
Page 10 Explanation of “Memory” is partly revised.
Page 10 Figure 1.3.1 is partly revised.
Page 22 Figure 1.7.1 is partly revised.
Page 23 Figure 1.7.2 is partly revised.
Page 23 “Internal Reserved Area Expansion Bit (PM13)” is added.
Page 24 Figure 1.7.3 is partly revised.
Page 25 Explanation of “(3) Selecting separate/multiplex bus” is partly revised.
Page 28 Explanation of “(2) Chip select signal” is partly added.
Page 29 Figure 1.9.2 is added.
Page 37 Explanation of “(2) Sub-clock” is partly revised.
Page 38 Figure 1.10.4 is partly revised.
Page 39 Explanation of “Stop Mode” is partly revised.
Page 39 Table 1.10.2 is partly revised.
Page 40 Explanation of “Wait Mode” is partly revised.
Page 40 Table 1.10.3 is partly revised.
Page 42 Explanation of “Power Control” is partly revised.
Page 62 Explanation of “Address Match Interruptl” is partly revised.
Revision history
M16C/62A Group data sheet
00.7.10
01.3.27
270