MH64D72KLG-75 Datasheet, PDF (27/38 Pages) Mitsubishi Electric Semiconductor – 4,831,838,208-BIT (67,108,864-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module

Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH64D72KLG-75,-10
4,831,838,208-BIT (67,108,864-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module
Module input and output timing. Read Interrupted by Precharge (BL=8)
/CLK
CLK
Command
READ
PRE
DQS
Module
CL=3.0
Discrete
CL=2.0
DQ
Command
DQS
DQ
Command
READ
PRE
Q0 Q1 Q2 Q3 Q4 Q5
READ PRE
Q0 Q1 Q2 Q3
DQS
DQ
Q0 Q1
MIT-DS-0389-1.1
MITSUBISHI ELECTRIC
20.Nov.2000
27