MH32D72KLH-75 Datasheet, PDF (27/39 Pages) Mitsubishi Electric Semiconductor – 2,415,919,104-BIT (33,554,432-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module

Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH32D72KLH-75,-10
2,415,919,104-BIT (33,554,432-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module
Module input and output timing. Read Interrupted by Precharge (BL=8)
/CLK
CLK
Command
READ
PRE
Module
CL=3.0
Discrete
CL=2.0
DQS
DQ
Command
DQS
DQ
Command
READ
PRE
Q0 Q1 Q2 Q3 Q4 Q5
READ PRE
Q0 Q1 Q2 Q3
DQS
DQ
Q0 Q1
MIT-DS-0391-1.0
MITSUBISHI ELECTRIC
24.Nov.2000
27