MH32S72PHB-7 Datasheet, PDF (25/55 Pages) Mitsubishi Electric Semiconductor – 2415919104-BIT (33554432 - WORD BY 72-BIT)SynchronousDRAM

Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH32S72PHB -7,-8,-10
2415919104-BIT (33554432 - WORD BY 72-BIT)SynchronousDRAM
[ Write Interrupted by Write ]
Burst write operation can be interrupted by new write of the same or the other bank.
Random column access is allowed. WRITE to WRITE interval is minimum 1 CK.
CK
Command
A0-9
A10
A11
BA0,1
DQ
Write Interrupted by Write (BL=4)
Write Write
Yi Yj
00
Write
Yk
0
Write
Yl
0
00 00
10
00
Dai0 Daj0 Daj1 Dbk0 Dbk1 Dbk2 Dal0 Dal1 Dal2 Dal3
[ Write Interrupted by Read ]
Burst write operation can be interrupted by read of the same or the other bank.
Random column access is allowed. WRITE to READ interval is minimum 1 CK. The
input data on DQ at the interrupting READ cycle is "don't care".
Write Interrupted by Read (BL=4, CL=3)
CK
Command
A0-9,11
A10
A11
BA0,1
Write READ
Yi Yj
00
00 00
Write
Yk
0
READ
Yl
0
10
00
DQMB0-7
DQ
Dai0
Qaj0 Qaj1
Dbk0 Dbk1
Qbl0
MIT-DS-0296-0.0
MITSUBISHI
ELECTRIC
( 25 / 55 )
7/Jan. /1999