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| M37532M4 Datasheet, PDF (25/50 Pages) Mitsubishi Electric Semiconductor – SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER | |||
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MITSUBISHI MICROCOMPUTERS
7532 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
b7
b0
USB transmit data byte number set register 0
(EP0BYTE: address 002116)
Set a number of data byte for transmitting with endpoint 0.
CPU read: Enabled
CPU write: Set/Clear
Hardware read: Used
Hardware write: Not used
Not used (return â0â when read)
b7
b0
USB transmit data byte number set register 1
(EP1BYTE: address 002216)
Set a number of data byte for transmitting with endpoint 1.
CPU read: Enabled
CPU write: Set/Clear
Hardware read: Used
Hardware write: Not used
Not used (return â0â when read)
b7
b0
USB PID control register 0
(EP0PID: address 002316)
Not used (return â1â when read)
Endpoint 0 enable flag
0: Endpoint 0 invalid
1: Endpoint 0 valid
CPU read: Enabled
CPU write: Set/Clear
Hardware read: Used
Hardware write: Not used
Endpoint 0 PID selection flag
1xxx: IN token interrupt of DATA0/1 is valid
01xx: STALL handshake is valid for IN token
00xx: NACK handshake is valid for IN token
xxx1: STALL handshake is valid for OUT token
xx10: ACK handshake is valid for OUT token
xx00: NACK handshake is valid for OUT token
x: any data
b4, b5, b6
CPU read: Enabled
CPU write: Set/Clear
Hardware read: Used
Hardware write: Not used
b7
CPU read: Enabled
CPU write: Set/Clear
Hardware read: Used
Hardware write: Clear
b7
b0
USB PID control register 1
(EP1PID: address 002416)
Not used (return â1â when read)
Endpoint 1 PID selection flag
1x: IN token interrupt of DATA0/1 is valid
01: STALL handshake is valid for IN token
00: NACK handshake is valid for IN token
x: any data
b6
CPU read: Enabled
CPU write: Set/Clear
Hardware read: Used
Hardware write: Not used
b7
CPU read: Enabled
CPU write: Set/Clear
Hardware read: Used
Hardware write: Clear
b7
b0
USB address register
(USBA: address 002516)
Set an address allocated by the USB host.
CPU read: Disabled
CPU write: Set/Clear
Hardware read: Used
Hardware write: Not used
Not used (returns â1â when read)
Fig. 28 Structure of serial I/O1-related registers (3)
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