MH8S72DALD-6 Datasheet, PDF (23/55 Pages) Mitsubishi Electric Semiconductor – 603979776-BIT (8388608 - WORD BY 72-BIT)Synchronous DRAM

Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8S72DALD -6,-7,-8
603979776-BIT (8388608 - WORD BY 72-BIT)Synchronous DRAM
[ Write Interrupted by Write ]
Burs t write operation can be interrupted by new write of any active bank. Random
column access is allowed. WRITE to WRITE interval is minimum 1 CK.
Write Interrupted by Write (BL=4)
CK
Command
A0-9, 11
A10
BA0,1
Write
Ya
0
00
Write Write
Yb Yc
0
0
00 10
DQ
Da0 Da1 Da2 Db0 Dc0 Dc1 Dc2 Dc3
[ Write Interrupted by Read ]
Burs t write operation can be interrupted by read of any active bank. Random column
access is allowed. WRITE to READ interval is minimum 1 CK. The input data on DQ
at the interrupting READ cycle is "don't care".
Write Interrupted by Read (BL=4, CL=2)
CK
Command ACT
Write
READ
A0-9,11 Xa
A10 Xa
BA0,1 00
DQ
Ya
Yb
0
0
00
00
Da0 Da1
Qb0 Qb1 Qb2 Qb3
don't care
MIT-DS-0341-0.0
MITSUBISHI
ELECTRIC
( 23 / 55 )
17.Sep.1999