MH4S64CZTJ-12 Datasheet, PDF (23/45 Pages) Mitsubishi Electric Semiconductor – 268435456-BIT (4194304-WORD BY 64-BIT)SynchronousDRAM

Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH4S64CZTJ/CWZTJ-12,-15,-1539
268435456-BIT (4194304-WORD BY 64-BIT)SynchronousDRAM
[ Write Interrupted by Precharge ]
Burst write operation can be interrupted by precharge of the same bank. Random
column access is allowed. Because the write recovery time(tWR) is required between
the last input data and the next PRE, 3rd data should be masked with DQMB0-7
shown as below.
Write Interrupted by Precharge (BL=4)
CK
Command
A0-9
Write
Yi
PRE
tWR
ACT
tRP
Xb
A10
0
0
Xb
BA
0
0
0
DQMB0-7
DQ
Dai0 Dai1
This data should be masked to satisfy tWR requirement.
[ Write Interrupted by Burst Terminate ]
Burst terminate command can terminate burst write operation. In this case, the write
recovery time is not required and the bank remains active. The figure below shows
the case 3 words of data are written. Random column access is allowed. WRITE to
TERM interval is minimum 1 CK.
CK
Command
A0-9
A10
BA
DQMB0-7
DQ
Write Interrupted by Burst Terminate (BL=4)
Write
Yi
0
0
TERM
Dai0 Dai1 Dai2
MIT-DS-0044-0.3
MITSUBISHI
ELECTRIC
( 23 / 45 )
Oct.17.1996