M2S56D20ATP Datasheet, PDF (21/40 Pages) Elpida Memory – 256M Double Data Rate Synchronous DRAM

DDR SDRAM
(Rev.1.44)
Mar. '02
MITSUBISHI LSIs
M2S56D20/ 30/ 40ATP -75AL, -75A, -75L, -75, -10L, -10
M2S56D20/ 30/ 40AKT -75AL, -75A, -75L, -75, -10L, -10
256M Double Data Rate Synchronous DRAM
AC TIMING REQUIREMENTS(Continued)
(Ta=0 ~ 70^oC, VDD = VDDQ = 2.5V +0.2V, VSS = VSSQ = 0V, unless otherwise noted)
Symbol
AC Characteristics Parameter
tRAS Row Active time
tRC Row Cycle time(operation)
tRFC Auto Ref. to Active/Auto Ref. command period
tRCD Row to Column Delay
tRP Row Precharge time
tRRD Act to Act Delay time
tWR Write Recovery time
tDAL Auto Precharge write recovery + precharge time
tWTR Internal Write to Read Command Delay
tXSNR Exit Self Ref. to non-Read command
tXSRD Exit Self Ref. to -Read command
tXPNR Exit Power down to command
tXPRD Exit Power down to -Read command
tREFI Average Periodic Refresh interval
-75A
-75
-10
Min.
Max
Min.
Max
Min.
Max
Unit
45 120,000 45 120,000 50 120,000 ns
65
65
70
ns
75
75
80
ns
20
20
20
ns
20
20
20
ns
15
15
15
ns
15
15
15
ns
35
35
35
ns
1
1
1
tCK
75
75
80
ns
200
200
200
tCK
1
1
1
tCK
1
1
1
tCK
7.8
7.8
7.8
us
Notes
18
17
Output Load Condition
VOUT
VTT =VREF
50W
Zo=50W
30pF
VREF
DQS
DQ
Output Timing
Measurement
Reference Point
VREF
VREF
CAPACITANCE
(Ta=0 ~ 70^oC, VDD = VDDQ = 2.5V + 0.2V, VSS = VSSQ = 0V, unless otherwise noted)
Symbol
Parameter
Limits
Delta
Test Condition
Min.
Max.
Cap.(Max.)
Unit
Notes
CI(A)
CI(C)
Input Capacitance, address pin
Input Capacitance, control pin
VI=1.25v 2.0 3.0
f=100MHz 2.0 3.0
0.50
pF 11
pF 11
CI(K)
Input Capacitance, CLK pin
VI=25mVrms 2.0 3.0
0.25
pF 11
CI/O I/O Capacitance, I/O, DQS, DM pin
4.0 5.0
0.50
pF 11
MITSUBISHI ELECTRIC
21