MH16S64PHC-7 Datasheet, PDF (20/55 Pages) Mitsubishi Electric Semiconductor – 1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM

Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH16S64PHC -7,-8, -10
1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM
WRITE
After tRCD from the bank activation, a WRITE command can be issued. 1st input data is set
at the same cycle as the WRITE. Following(BL-1) data are written into the RAM, when the
Burst Length is BL. The start address is specified by A8-0, and the address sequence of burst
data is defined by the Burst Type. A WRITE command may be applied to any active bank, so
the row precharge time(tRP) can be hidden behind continuous input data by interleaving the
multiple banks. From the last input data to the PRE command, the write recovery time (tWR) is
required. When A10 is high at a WRITE command, the auto-precharge(WRITEA) is
performed. Any command(READ, WRITE, PRE, ACT) to the same bank is inhibited till the
internal precharge is complete. The internal precharge begins at tWR after the last input data
cycle. The next ACT command can be issued after tRP from the internal precharge timing.
The Mode Register can be WRITE command is issued and the remaining burst length is
ignored.The read data burst length os unaffected while in this mode.
CK
Command
A0-9
A10
A11
BA0,1
DQ
CK
Command
A0-9
A10
A11
BA0,1
DQ
MIT-DS-0299-0.0
Multi Bank Interleaving WRITE (BL=4)
ACT
Xa
Xa
Xa
00
tRCD
Write ACT
Y Xb
tRCD
Write PRE
Y
PRE
0 Xb
0
0
0
Xb
0
0
00 10
10 00
10
Da0 Da1 Da2 Da3 Db0 Db1 Db2 Db3
WRITE with Auto-Precharge (BL=4)
ACT
Xa
Xa
Xa
00
Write
tRCD
tWR
Y
1
00
Da0 Da1 Da2 Da3
ACT
tRP
Xa
Xa
Xa
00
Internal precharge begins
MITSUBISHI
ELECTRIC
( 20 / 55 )
11/ Jan. /1999