M66332FP Datasheet, PDF (2/43 Pages) Mitsubishi Electric Semiconductor – FACSIMILE IMAGE DATA PROCESSOR

MITSUBISHI 〈DIGITAL ASSP〉
M66332FP
FACSIMILE IMAGE DATA PROCESSOR
BLOCK DIAGRAM
System Clock
SYSCK
8
ADC Analog
Vcc
AVCC
18
ADC Logic
Vcc
DVCC
29
VCC
10 35 46 55
PTIM 15
SH 56
Sensor
Interface
CK1 2
CK2 1
RS 3
CLAMP 4
Analog _{S/H 5}
Signal
Interface
AGC 16
DSCH 17
Image Processing Sequence Control Signal
Sensor Control To each
block
Analog Control
Correction memory
(304 words × 5bits)
Detection
of Image
Data Area
Separation
of Image
Data Area
Simple Bi-level
Conversion/Background
and object Level Detection
Convert
to
bi-level
Cur out/
Scale
down
DMA Control
Uniformity Correction
ASIG 27
5bit A-D converter
(flash type)
SRAM 16
words
× 4bits
Collective
Dithering
(16 levels)
MPU Bus Interface
20 21 23 24 25
VBL VML2 VWL
VML1 VML3
ADC Reference Voltage
19
AGND
ADC
Analog GND
30 6 22 36 45 51 52
DGND
ADC
Logic GND
GND
14 SRDY
13 STIM CODEC
12 SCLK ^Interface
11 SVID
54 DAK DMA
53 DRQ ^Interface
50 RESET
47 CS
48 RD
MPU
Interface
49 WR
31 A0 MPU
Interface
34 A3 _(Address)
37 D0 _MPU
44 D7 ^Interface
(Data)
Table 1 Image Processing Functions
Image Processing Function
Specifications
Remarks
Read Width
• A4, B4, A3
Resolution
• 8 pixels/mm (primary scanning direction)
Read speed
• 5ms/line Typ. 2ms/line maximum
• Operated with system clock and PRE_DATA
(registers 2, 3)
Uniformity Correction
• White correction only
• Block correction in units of 8 pixels
• 50% Correction range
• Built-in SRAM as correction memory (304 words ×
5bits) (read/write allowed from MPU)
MTF Compensation
• Laplacian filter circuit for 3 × 1 pixels in current line
(1 dimension)
• No need for compensation memory
Simple Bi-level Conversion
• Floating threshold method using background and
object level detection circuit
Pseudo half-tone
• Dither method: 16 levels (4 × 4matrix)
• Built-in SRAM as dither memory (16 words × 4bits)
(read/write allowed from MPU)
Separation of Image Data
Area
• Detection by brightness difference in 5 × 1 pixels
area in current line
• No need for processing memory
Scale down
• Selection method • Scale down: A3 → B4 set
to 13/15; B4 → A4, 9/11; A3 → A4, 12/17
γ Correction
• Logarithmic correction
• Apply external voltage (resistor connection is also
allowed) to A-D converter middle basic supply
voltage pins.
Image Sensor Control Signal
• Control signal generation for contact sensor (CIS)
and scale down CCD
Analog Signal Processing
• Generate control signals for external CLAMP
circuit, sample/hold circuit, and AGC circuit
• Built-in 5-bit flash A-D converter
2