MH8S64DBKG-6 Datasheet, PDF (19/51 Pages) Mitsubishi Electric Semiconductor – 536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM

Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8S64DBKG -6,-6L-7,-7L,-8,-8L
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
WRITE
A WRITE command can be issued to any active bank. The start address is specified by A0-7
(x16). 1st input data is set at the same cycle as the WRITE. The consecutive data length to
be written is defined by the Burst Length. The address sequence of burst data is defined by
the Burst Type. Minimum delay time of a WRITE command after an ACT command to the
same bank is tRCD. From the last input data to the PRE command, the write recovery time
(tWR) is required. When A10 is high at a WRITE command, auto-precharge (WRITEA) is
performed. Any command (READ, WRITE, PRE, ACT, TBST) to the same bank is inhibited till
the internal precharge is complete. The internal precharge starts at tWR after the last input
data cycle. The next ACT command can be issued after (BL + tWR -1 + tRP) from the
previous WRITEA. In any case, tRCD + BL + tWR -1 > tRASmin must be met.
WRITE (BL=4)
CK
Command ACT
Write
tRCD
BL
A0-9, 11 Xa
Ya
A10 Xa
0
PRE
tRP
ACT
Xa
0
Xa
BA0,1 ₀₀
00
00
tWR
DQ
Da0 Da1 Da2 Da3
WRITE with Auto-Precharge (BL=4)
CK
Command ACT
Write
tRCD
BL
A0-9, 11 Xa
Ya
A10 Xa
1
BA0,1 ₀₀
DQ
00
tWR
Da0 Da1 Da2 Da3
ACT
tRP
Xa
Xa
00
MIT-DS-0340-0.3
Internal precharge begins
MITSUBISHI
ELECTRIC
( 19 / 51 )
27.Mar.2001