M37905F8CFP Datasheet, PDF (17/34 Pages) Mitsubishi Electric Semiconductor – 16-BIT CMOS MICROCOMPUTER

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MITSUBISHI MICROCOMPUTERS
M37905F8CFP, M37905F8CSP
16-BIT CMOS MICROCOMPUTER
CPU Reprogramming Mode
The CPU reprogramming mode is used to perform the operations for
the internal flash memory (reading, programming, erasing) under
control of the CPU.
In this mode, only the user ROM area can be reprogrammed; the
boot ROM area cannot be reprogrammed.
The user-original reprogramming control software for the CPU repro-
gramming mode can be stored in either the user ROM area or the
boot ROM area.
Because the CPU cannot read out the flash memory in the CPU re-
programming mode, the above software must be transferred to the
internal RAM in advance to be executed.
Boot Mode
The user-original reprogramming control software for the CPU repro-
gramming mode must be stored into the user ROM area or the boot
ROM area in the flash memory parallel I/O mode in advance. (If this
program has been stored into the boot ROM area, the flash memory
serial I/O mode will become unavailable).
Note that addresses of the boot ROM area depend on the accessing
ways to the boot ROM area, When accessing in the flash memory
parallel I/O mode, these addresses will be shifted to 000016 to
1FFF16. On the other hand, when accessing with the CPU, these ad-
dresses will be shifted to E00016 to FFFF16.
Reset removal with both of the MD0 and MD1 pins held “L” invokes
the normal microcomputer mode, and the CPU operates using the
control software stored in the user ROM area. In this case, the boot
ROM area is not accessible.
Removing reset with the MD0 pin held “L” and the MD1 pin “H”, the
CPU starts its operation using the reprogramming control software
stored in the boot ROM area. This mode is called the boot mode. The
reprogramming control software in the boot ROM area can also re-
program the user ROM area.
After reset removal, be sure not to change the status at pins MD0
and MD1.
7 6 5 4 3 21 0
Flash memory control register
Address
9E16
RY/BY status bit
0: Busy (Programming or erasing is active.)
1: Ready
CPU reprogramming mode select bit (Note 2)
0: Normal mode (Software commands are ignored.)
1: CPU reprogramming mode (Software commands are acceptable.)
Flash memory reset bit (Note 3)
0: Normal operation
1: Reset
User ROM area select bit (Note 4)
(Valid only in the boot mode.)
0: Boot ROM area access
1: User ROM area access
Notes 1: The contents of the flash memory control register after reset is removed are “XX000001”.
2: To set “1”, writing of “0” to bit 1 and subsequent writing of “1” to bit 1 are necessary. Writing to bit 1 must be
performed by the user-original reprogramming control software in the internal RAM.
3: This bit is valid only when bit 1 = “1”. Before setting this bit to “0”, be sure to confirm that bit 0 = “1” after
setting this bit to “1” (reset). This bit 3 must be controlled with bit 1 = “1”.
4: Writing to bit 5 must be performed by the user-original reprogramming control software in the internal RAM.
Fig. 7 Bit configuration of flash memory control register
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