MH32D72AKLB-75 Datasheet, PDF (16/40 Pages) Mitsubishi Electric Semiconductor – 2,415,919,104-BIT (33,554,432-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module

Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH32D72AKLB-75,-10
2,415,919,104-BIT (33,554,432-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module
ABSOLUTE M AXIMUM RATINGS
Symbol
Parameter
Conditions
Ratings
Unit
Vdd
Supply Voltage
with respect to Vss
-0.5 ~ 3.7
V
VddQ Supply Voltage for Output with respect to VssQ
-0.5 ~ 3.7
V
VI
Input Voltage
with respect to Vss -0.5 ~ Vdd+0.5
V
VO
Output Voltage
with respect to VssQ -0.5 ~ VddQ+0.5 V
IO
Output Current
50
mA
Pd
Power Dissipation
Ta = 25°C
20
W
Topr
Operating Temperature
0 ~ 70
°C
T stg
Storage Temperature
-40 ~ 100
°C
DC OPERATING CONDITIONS
(Ta=0 ~ 70°C , unless otherwise noted)
Symbol
Parameter
Min.
Limits
Typ.
Vdd/VddQ
Supply Voltage
2.3
2.5
Vref
Input Reference Voltage
1.15
1.25
VIH(DC)
High-Level Input Voltage
Vref + 0.18
VIL(DC)
Low-Level Input Voltage
-0.3
VIN(DC) Input Voltage Level, CK0 and /CK0
-0.3
VID(DC) Input Differential Voltage, CK0 and /CK0 0.36
VTT
I/O Termination Voltage
Vref - 0.04
Max.
Unit Notes
2.7
V
1.35
V
5
VddQ+0.3 V
Vref - 0.18 V
VddQ + 0.3 V
VddQ + 0.6 V
7
Vref + 0.04 V
6
CAPACITANCE
(Ta=0 ~ 70°C , Vdd = VddQ = 2.5 ± 0.2V, Vss = VssQ = 0V, unless otherwise noted)
Symbol
Parameter
Test Condition
CI(A) Input Capacitance, address pin
CI(C) ^{Input Capacitance, control pin}
CI(K) Input Capacitance, CK0 pin
CI/O ^{Input Capacitance, I/O pin}
VI - 1.25V
f =100MHz
VI = 25mVrm
Limits(max.)
11.0
11.0
38.0
22.0
Unit ^Notes
pF 11
pF ₁₁
pF ₁₁
pF ₁₁
MIT-DS-0399-0.2
MITSUBISHI ELECTRIC
21.Mar.2001
16