MH1S64CWXTJ-12 Datasheet, PDF (15/45 Pages) Mitsubishi Electric Semiconductor – 67108864-BIT (1048576-WORD BY 64-BIT)SynchronousDRAM

Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH1S64CWXTJ-12,-15,-1539
67108864-BIT (1048576-WORD BY 64-BIT)SynchronousDRAM
OPERATION DESCRIPTION
BANK ACTIVATE
The SDRAM has two independent banks. Each bank is activated by the ACT command with
the bank address(BA). A row is indicated by the row address A10-0. The minimum activation
interval between one bank and the other bank is tRRD.
PRECHARGE
The PRE command deactivates indicated by BA. When both banks are active, the precharge
all command(PREA,PRE + A10=H) is available to deactivate them at the same time. After tRP
from the precharge, an ACT command can be issued.
CK
Command
A0-9
A10
BA
DQ
Bank Activation and Precharge All (BL=4, CL=3)
ACT
ACT READ
tRRD
Xa
Xb Y
tRCD
Xa
Xb 0
0
10
tRAS
PRE
tRP
1
Qa0 Qa1 Qa2 Qa3
ACT
Xb
Xb
1
Precharge all
READ
After tRCD from the bank activation, a READ command can be issued. 1st output date is
available after the /CAS Latency from the READ, followed by (BL-1) consecutive date when
the Burst Length is BL. The start address is specified by A7-0, and the address sequence of
burst data is defined by the Burst Type. A READ command may be applied to any active bank,
so the row precharge time(tRP) can be hidden behind continuous output data(in case of BL=8)
by interleaving the dual banks. When A10 is high at a READ command, the
auto-precharge(READA) is performed. Any command (READ, WRITE, PRE, ACT) to the
same bank is inhibited till the internal precharge is complete. The internal precharge start
timing depends on /CAD Latency. The next ACT command can be issued after tRP from the
internal precharge timing.
MIT-DS-0064-0.2
MITSUBISHI
ELECTRIC
( 15 / 45 )
Oct.28.1996