MH16S64BAMD-7 Datasheet, PDF (14/55 Pages) Mitsubishi Electric Semiconductor – 1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM

Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH16S64BAMD -7,-8,-10
1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM
[ /CAS LATENCY]
/CAS latency,CL,is used to synchronize the first output data with the CLK frequency,i.e.,the
speed of CLK determines which CL should be used.First output data is available after CL
cycles from READ command.
/CAS Latency Timing(BL=4)
CK
Command
Address
DQ
DQ
ACT
X
tRCD
READ
Y
CL=2
Q0 Q1 Q2 Q3
CL=3
Q0 Q1 Q2 Q3
CL=2
CL=3
[ BURST LENGTH ]
The burst length,BL,determines the number of consecutive wrutes or reads that will be
automatically performed after the initial write or read command.For BL=1,2,4,8,full page the
output data is tristated(Hi-Z) after the last read.For BL=FP (Full Page),the TBST (Burst
Terminate) command should be issued to stop the output of data.
Burst Length Timing(CL=2)
tRCD
CK
Command
ACT
READ
Address
X
Y
DQ
Q0
BL=1
DQ
Q0 Q1
BL=2
DQ
Q0 Q1 Q2 Q3
BL=4
DQ
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
BL=8
DQ
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8
Qm Q0 Q1 ^BL=FP
MIT-DS-0212-0.4
m=511
MITSUBISHI
ELECTRIC
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29. Oct.1998