M37733S4BFP Datasheet, PDF (14/36 Pages) Mitsubishi Electric Semiconductor – 16-BIT CMOS MICROCOMPUTER

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MITSUBISHI MICROCOMPUTERS
M37733S4BFP
16-BIT CMOS MICROCOMPUTER
RESET CIRCUIT
_____
The microcomputer is released from the reset state when the RESET
pin is returned to “H” level after holding it at “L” level with the power
source voltage at 5 V ± 10 %. Program execution starts at the address
formed by setting address A23 – A16 to 0016, A15 – A8 to the contents
of address FFFF16, and A7 – A0 to the contents of address FFFE16.
Figure 12 shows the status of the internal registers during reset.
Figure 13 shows an example of a reset circuit. If the stabilized clock
is input from the external to the main-clock oscillation circuit, the reset
input voltage must be 0.9 V or less when the power source voltage
reaches 4.5 V. If a resonator/oscillator is connected to the main-clock
oscillation circuit, change the reset input voltage from “L” to “H” after
the main-clock oscillation is fully stabilized.
Port P0 direction register
Address
(0416)•••
0016
Port P1 direction register
(0516)•••
0016
Port P2 direction register
Port P3 direction register
Port P4 direction register
Port P5 direction register
(0816)•••
(0916)•••
(0C16)•••
(0D16)•••
0016
00 00
0016
0016
Port P6 direction register
(1016)•••
0016
Port P7 direction register
(1116)•••
0016
Port P8 direction register
A-D control register 0
A-D control register 1
UART 0 transmit/receive mode register
(1416)•••
0016
(1E16)••• 0 0 0 0 0 ? ? ?
(1F16)•••
00 0 11
(3016)•••
0016
UART 1 transmit/receive mode register (3816)•••
0016
UART 0 transmit/receive
control register 0
UART 1 transmit/receive
control register 0
UART 0 transmit/receive
control register 1
UART 1 transmit/receive
control register 1
Count start flag
(3416)••• 0 0 0 0 1 0 0 0
(3C16)••• 0 0 0 0 1 0 0 0
(3516)••• 0 0 0 0 0 0 1 0
(3D16)••• 0 0 0 0 0 0 1 0
(4016)•••
0016
One- shot start flag
(4216)•••
0000 0
Up-down flag
(4416)•••
0016
Timer A0 mode register
Timer A1 mode register
Timer A2 mode register
Timer A3 mode register
(5616)•••
(5716)•••
(5816)•••
(5916)•••
0016
0016
0016
0016
Timer A4 mode register
(5A16)•••
0016
Timer B0 mode register
(5B16)••• 0 0 1 0 0 0 0 0
Timer B1 mode register
(5C16)••• 0 0 1 0 0 0 0
Timer B2 mode register
Processor mode register 0
Processor mode register 1
(5D16)••• 0 0 1 0 0 0 0
(5E16)•••
0016
(5F16)•••
0
Watchdog timer register
(6016)•••
FFF16
Address
Watchdog timer frequency selection flag (6116)•••
0
Waveform output mode register
(6216)••• 0 0 0 0 0 0
UART2 transmit/receive mode register
(6416)••• 0 0 0 0 0 0 0
UART2 transmit/receive control register 0 (6816)•••
1000
UART2 transmit/receive control register 1
Oscillation circuit control register 0
Port function control register
Serial transmit control register
(6916)••• 0 0 0 0 0 0 1 0
(6C16)••• 0 0 0 0 0 1
(6D16)•••
0016
(6E16)•••
00
Oscillation circuit control register 1
A-D/UART2 trans./rece. interrupt control register
(6F16)••• 0
(7016)•••
000 00
00 00
UART 0 transmission interrupt control register (7116)•••
00 00
UART 0 receive interrupt control register (7216)•••
00 00
UART 1 transmission interrupt control register (7316)•••
00 00
UART 1 receive interrupt control register (7416)•••
00 00
Timer A0 interrupt control register
(7516)•••
00 00
Timer A1 interrupt control register
(7616)•••
00 00
Timer A2 interrupt control register
(7716)•••
00 00
Timer A3 interrupt control register
(7816)•••
00 00
Timer A4 interrupt control register
(7916)•••
00 00
Timer B0 interrupt control register
(7A16)•••
00 00
Timer B1 interrupt control register
(7B16)•••
00 00
Timer B2 interrupt control register
(7C16)•••
00 00
INT0 interrupt control register
(7D16)•••
0000 00
INT1 interrupt control register
(7E16)•••
0000 00
INT2/Key input interrupt control register
(7F16)•••
0000 00
Processor status register (PS)
000 ? ?0001 ??
Program bank register (PG)
0016
Program counter (PCH)
Content of FFFF16
Program counter (PCL)
Content of FFFE16
Direct page register (DPR)
000016
Data bank register (DT)
0016
Contents of other registers and RAM are undefined during reset. Initialize them by software.
Fig. 12 Microcomputer internal status during reset
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