M6MGB162S4BVP Datasheet, PDF (13/29 Pages) Mitsubishi Electric Semiconductor – 16,777,216-BIT (1,048,576 -WORD BY 16-BIT ) CMOS 3.3V-ONLY FLASH MEMORY

MITSUBISHI LSIs
M6MGB/T162S4BVP
16,777,216-BIT (1,048,576 -WORD BY 16-BIT ) CMOS
3.3V-ONLY FLASH MEMORY &
4,194,304-BIT (524,288-WORD BY 8-BIT) CMOS SRAM
Stacked-MCP (Multi Chip Package)
Vcc POWER UP / DOWN TIMING
3.3V
F-VCC
GND
F-RP# ^VIH
VIL
Read /Write Inhibit
tVCS
F-CE# ^VIH
VIL
tPS
WE# ^VIH
VIL
Read /Write Inhibit
tPS
Read /Write Inhibit
AC WAVEFORMS FOR READ OPERATION AND TEST CONDITIONS
VIH
ADDRESSES
VIL
VIH
F-CE#
VIL
OE#
VIH
VIL
WE#
DATA
VIH
VIL
VOH
VOL
F-RP# ^VIH
VIL
HIGH-Z
tPS
ADDRESS VALID
tRC
ta (AD)
tRE
ta (CE)
tDF(CE)
tOEH
tCLZ
ta (OE)
tOLZ
tDF(OE)
tOH
OUTPUT VALID
tPHZ
AC WAVEFORMS FOR WRITE FFH or 71H AND READ OPERATION
HIGH-Z
TEST CONDITIONS
FOR AC CHARACTERISTICS
Input voltage : VIL = 0V, VIH = 3.0V
Input rise and fall times : £5ns
Reference voltage
at timing measurement : 1.5V
Output load : 1TTL gate +
CL(30pF)
or
DUT
1.3V
1N914
3.3kW
CL =30pF
VIH
ADDRESSES
VIL
VIH
F-CE#
VIL
OE#
WE#
DATA
F-RP#
VIH
VIL
tRE
VIH
VIL
VOH _HIGH-Z
VOL
VIH
FFH or 71H
Valid
tPS
VIL
ADDRESS VALID
tRC
ta (AD)
ta (CE)
tDF(CE)
tCLZ
ta (OE)
tOLZ
tDF(OE)
tOH
OUTPUT VALID
tPHZ
HIGH-Z
In the case of use F-CE# is Low fixed, it is allowed to define a timming specification of tRE
from rising edge of WE# to falling edge of OE#, and valid data is read after spec of tRE+ta(CE).
(This is only for FFH,71H program and read)
13
Sep. 1999 , Rev.2.0