M37736M4L Datasheet, PDF (12/32 Pages) Mitsubishi Electric Semiconductor – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

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MITSUBISHI MICROCOMPUTERS
M37736M4LXXXHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
ELECTRICAL CHARACTERISTICS (Vcc = 5 V, Vss = 0 V, Ta = –40 to +85 °C, unless otherwise noted)
Symbol
Parameter
Test conditions
VCC = 5 V,
f(XIN) = 12 MHz (square waveform),
(f(f2) = 6 MHz),
f(XCIN) = 32.768 kHz,
in operating (Note 1)
Limits
Min.
Typ.
Max.
Unit
4.5
9
mA
VCC = 3 V,
f(XIN) = 12 MHz (square waveform),
(f(f2) = 6 MHz),
f(XCIN) = 32.768 kHz,
in operating (Note 1)
3
6
mA
VCC = 3 V,
f(XIN) = 12 MHz (square waveform),
When single-chip ^{(f(f2) = 0.75 MHz),}
ICC
Power source mode, output pins ^{f(XCIN) : Stopped,}
current
are open, and
in operating
other pins are VSS. VCC = 3 V,
f(XIN) = 12 MHz (square waveform),
f(XCIN) = 32.768 kHz,
when a WIT instruction is executed (Note 2)
0.4
0.8
mA
6
12
µA
VCC = 3 V,
f(XIN) : Stopped,
f(XCIN) = 32.768 kHz,
in operating (Note 3)
30
60
µA
VCC = 3 V,
f(XIN) : Stopped,
f(XCIN) = 32.768 kHz,
when a WIT instruction is executed (Note 4)
Ta = 25 °C,
when clock is stopped
Ta = 85 °C,
when clock is stopped
3
6
µA
1
µA
20
µA
Notes 1. This applies when the main clock external input selection bit = “1”, the main clock division selection bit = “0”, and the signal output stop
bit = “1”.
2. This applies when the main clock external input selection bit = “1” and the system clock stop bit at wait state = “1”.
3. This applies when CPU and the clock timer are operating with the sub clock (32.768 kHz) selected as the system clock.
4. This applies when the XCOUT drivability selection bit = “0” and the system clock stop bit at wait state = “1”.
A–D CONVERTER CHARACTERISTICS
(VCC = AVCC = 5 V, VSS = AVSS = 0 V, Ta = –40 to +85 °C, f(XIN) = 12 MHz, unless otherwise noted (Note))
Symbol
Parameter
Test conditions
—
Resolution
VREF = VCC
—
Absolute accuracy
VREF = VCC
RLADDER
Ladder resistance
VREF = VCC
tCONV
Conversion time
VREF
Reference voltage
VIA
Analog input voltage
Note. This applies when the main clock division selection bit = “0” and f(f2) = 6 MHz.
Min.
10
19.6
2.7
0
Limits
Typ.
Max.
10
±3
25
VCC
VREF
Unit
Bits
LSB
kΩ
µs
V
V
12