M5M467400DTP-5 Datasheet, PDF (11/37 Pages) Mitsubishi Electric Semiconductor – FAST PAGE MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM

(Rev. 1.0)
MITSUBISHI LSIs
M5M467400/465400DJ,DTP -5,-6,-5S,-6S
M5M467800/465800DJ,DTP -5,-6,-5S,-6S
M5M465160DJ,DTP -5,-6,-5S,-6S
FAST PAGE MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM
FAST PAGE MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM
FAST PAGE MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
Write Cycle (Early Write and Delayed Write)
Symbol
Parameter
tWC
tRAS
tCAS
tCSH
tRSH
tWCS
tWCH
tCWL
tRWL
tWP
tDS
tDH
tOEH
Write cycle time
RAS low pulse width
CAS low pulse width
CAS hold time after RAS low
RAS hold time after CAS low
Write setup time before CAS low
(Note 23)
Write hold time after CAS low
CAS hold time after W low
RAS hold time after W low
Write pulse width
Data setup time before CAS low or W low
Data hold time after CAS low or W low
OE hold time after W low
Limits
M5M46X400D-5,5S M5M46X400D-6,6S
M5M46X800D-5,5S M5M46X800D-6,6S _Unit
M5M465160D-5,5S M5M465160D-6,6S
Min
Max
Min
Max
90
110
ns
50 10000
60 10000 ns
13 10000
15 10000 ns
50
60
ns
13
15
ns
0
0
ns
8
10
ns
13
15
ns
13
15
ns
8
10
ns
0
0
ns
8
10
ns
13
15
ns
Read-Write and Read-Modify-Write Cycles
Symbol
Parameter
tRWC
tRAS
tCAS
tCSH
tRSH
tRCS
tCWD
tRWD
tAWD
tCWL
tRWL
tWP
tDS
tDH
tOEH
Read write/read modify write cycle time
RAS low pulse width
CAS low pulse width
(Note22)
CAS hold time after RAS low
RAS hold time after CAS low
Read setup time before CAS low
Delay time, CAS low to W low
Delay time, RAS low to W low
Delay time, address to W low
CAS hold time after W low
RAS hold time after W low
(Note23)
(Note23)
(Note23)
Write pulse width
Data setup time before CAS low or W low
Data hold time after CAS low or W low
OE hold time after W low
Limits
M5M46X400D-5,5S M5M46X400D-6,6S
M5M46X800D-5,5S M5M46X800D-6,6S Unit
M5M465160D-5,5S M5M465160D-6,6S
Min
Max
Min
Max
126
150
ns
85 10000
95 10000 ns
50 10000
50 10000 ns
85
95
ns
50
50
ns
0
0
ns
30
30
ns
65
75
ns
40
45
ns
13
15
ns
13
15
ns
8
10
ns
0
0
ns
8
10
ns
13
15
ns
Note 22: tRWC is specified as tRWC(min)=tRAC(max)+tODD(min)+tRWL(min)+tRP(min)+4tT.
23: tWCS, tCWD, tRWD and tAWD and, tCPWD are specified as reference points only. If tWCS ≥ tWCS(min) the cycle is an early write cycle and the
DQ pins will remain high impedance throughout the entire cycle. If tCWD ≥ tCWD(min), tRWD ≥ tRWD (min), tAWD ≥ tAWD(min) and tCPWD ≥ tCPWD(min)
(for Fast Page mode cycle only), the cycle is a read-modify-write cycle and the DQ will contain the data read from the selected address.
If neither of the above condition (delayed write) is satisfied, the DQ (at access time and until CAS or OE goes back to VIH ) is indetermi-
nate.
11
Aug. 1999
MITSUBISHI ELECTRIC