M65675FP Datasheet, PDF (10/17 Pages) Mitsubishi Electric Semiconductor – DIGITAL NTSC/PAL ENCODER

PRELIMINARY
Notice:This is not a final specification.
Some parametric limits are subject to change.
MITSUBISHI ICs (TV)
M65675FP/M65676FP
DIGITAL NTSC/PAL ENCODER
Y and C Mixing Circuit
The analog outputs of D-A converters are filtered and then input to
the M65675FP again. The Y and C signals, whose maximum
amplitude is 0.6VP-P, are combined and the resulting composite
signal (CVBS) is output. The maximum amplitude of CVBS output is
1.2VP-P.
6-dB Amplifier
The M65675FP has three 6-dB amplifiers. The maximum input is
0.6VP-P and the resulting maximum output will be 1.24VP-P. The
maximum drivability and band width are 1mA and 6MHz,
respectively.
Operating Description
Initialize
After power-on, the M65675FP/M65676FP has two different
initialize sequences in the master and slave modes, respectively.
In the master mode, the internal registers are initialized responding
to the reset signal. After reset, the serial registers are set to the
default data and an internal control clock (13.5MHz) is generated
from the system clock.
In the slave mode, the internal registers are initialized the same as
in the master mode. The serial registers are set up to the default
data and the system clock generates the internal control clock (13.5
MHz) in the synchronization with the trailing edge of the horizontal
sync signal (H-sync), after reset. (Referring to Fig. 5)
In case the serial registers are set up to data other than the default
ones, the data should be renewed according to the I²C bus format
in both the master and slave modes, after reset.
·In the master modeÒ
System clock
(27.0MHz)
Reset
H-sync
·In the slave modeÒ
System clock
(27.0MHz)
Reset
H-sync
Generation starting timing
of reference clock
Generation starting timing
of reference clock
Fig. 5 GENERATION STARTING TIMING OF INTERNAL REFERENCE CLOCK
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