M5M467405DTP-5 Datasheet, PDF (10/39 Pages) Mitsubishi Electric Semiconductor – EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM

(Rev. 1.0)
MITSUBISHI LSIs
M5M467405/465405DJ,DTP -5,-6,-5S,-6S
M5M467805/465805DJ,DTP -5,-6,-5S,-6S
M5M465165DJ,DTP -5,-6,-5S,-6S
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
TIMING REQUIREMENTS (For Read, Write, Read-Modify-Write ,Refresh, and EDO Mode Cycles)
(Ta=0 ~ 70 C , Vcc=3.3 ±0.3V, Vss=0V, unless otherwise noted See notes 14,15)
Symbol
Parameter
tREF
tREF
tRP
tRCD
tCRP
tRPC
tCPN
tRAD
tASR
tASC
tRAH
tCAH
tDZC
tDZO
tRDD
tCDD
tODD
tWED
tT
Refresh cycle time
Refresh cycle time (S-version only)
RAS high pulse width
Delay time, RAS low to CAS low
(Note16)
Delay time, CAS high to RAS low
Delay time, RAS high to CAS low
CAS high pulse width
Column address delay time from RAS low
(Note17)
Row address setup time before RAS low
Column address setup time before CAS low _(Note18)
Row address hold time after RAS low
Column address hold time after CAS low
Delay time, data to CAS low
Delay time, data to OE low
Delay time, RAS high to data
Delay time, CAS high to data
(Note19)
(Note19)
(Note20)
(Note20)
Delay time, OE high to data
(Note20)
Delay time, W low to data
Transition time
(Note20)
(Note21)
Limits
M5M46X405D-5,5S M5M46X405D-6,6S _Unit
M5M46X805D-5,5S M5M46X805D-6,6S
M5M465165D-5,5S M5M465165D-6,6S
Min
Max
Min
Max
64
64
ms
128
128
ms
30
40
ns
14
37
14
45
ns
5
5
ns
0
0
ns
8
10
ns
10
25
12
30
ns
0
0
10
0
ns
0
13
ns
8
10
ns
8
10
ns
0
0
ns
0
0
ns
13
15
ns
13
15
ns
13
15
ns
13
15
ns
1
50
1
50
ns
Note 14: The timing requirements are assumed tT =2ns.
15: VIH(min) and VIL(max) are reference levels for measuring timing of input signals.
16: tRCD(max) is specified as a reference point only. If tRCD is less than tRCD(max), access time is tRAC. If tRCD is greater than tRCD(max), access
time is controlled exclusively by tCAC or tAA.
17: tRAD(max) is specified as a reference point only. If tRAD ≥ tRAD(max) and tASC ≤ tASC(max), access time is controlled exclusively by tAA.
18: tASC(max) is specified as a reference point only. If tRCD ≥ tRCD(max) and tASC ≥ tASC(max), access time is controlled exclusively by tCAC.
19: Either tDZC or tDZO must be satisfied.
20: Either tRDD or tCDD or tODD or tWED must be satisfied.
21: tT is measured between VIH(min) and VIL(max).
Read and Refresh Cycles
Symbol
Parameter
tRC
Read cycle time
tRAS
RAS low pulse width
tCAS
CAS low pulse width
tCSH CAS hold time after RAS low
tRSH RAS hold time after CAS low
tRCS Read Setup time before CAS low
tRCH Read hold time after CAS high
tRRH Read hold time after RAS high
tRAL
Column address to RAS hold time
tCAL
Column address to CAS hold time
tORH RAS hold time after OE low
tOCH CAS hold time after OE low
(Note 22)
(Note 22)
Limits
M5M46X405D-5,5S M5M46X405D-6,6S
M5M46X805D-5,5S M5M46X805D-6,6S ^Unit
M5M465165D-5,5S M5M465165D-6,6S
Min
Max
Min
Max
84
104
ns
50
10000
60
10000 ns
8
10000
10
10000 ns
35
40
ns
13
15
ns
0
0
ns
0
0
ns
0
0
ns
25
30
ns
13
18
ns
13
15
ns
13
15
ns
Note 22: Either tRCH or tRRH must be satisfied for a read cycle.
10
Aug. 1999
MITSUBISHI ELECTRIC