M5M467400BJ Datasheet, PDF (10/37 Pages) Mitsubishi Electric Semiconductor – FAST PAGE MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM

(Rev. 1.1)
MITSUBISHI LSIs
M5M467400/465400BJ,BTP -5,-6,-5S,-6S
M5M467800/465800BJ,BTP -5,-6,-5S,-6S
M5M465160BJ,BTP -5,-6,-5S,-6S
FAST PAGE MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM
FAST PAGE MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM
FAST PAGE MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
TIMING REQUIREMENTS (For Read, Write, Read-Modify-Write ,Refresh, and Fast-Page Mode Cycles)
(Ta=0 ~ 70 C , Vcc=3.3 ±0.3V, Vss=0V, unless otherwise noted See notes 13,14)
Symbol
Parameter
tREF
tREF
tRP
tRCD
tCRP
tRPC
tCPN
tRAD
tASR
tASC
tRAH
tCAH
tDZC
tDZO
tCDD
tODD
tT
Refresh cycle time
Refresh cycle time (S-version only)
RAS high pulse width
Delay time, RAS low to CAS low
(Note15)
Delay time, CAS high to RAS low
Delay time, RAS high to CAS low
CAS high pulse width
Column address delay time from RAS low
(Note16)
Row address setup time before RAS low
Column address setup time before CAS low _(Note17)
Row address hold time after RAS low
Column address hold time after CAS low
Delay time, data to CAS low
Delay time, data to OE low
Delay time, CAS high to data
(Note18)
(Note18)
(Note19)
Delay time, OE high to data
Transition time
(Note19)
(Note20)
Limits
M5M46X400B-5,5S M5M46X400B-6,6S _Unit
M5M46X800B-5,5S M5M46X800B-6,6S
M5M465160B-5,5S M5M465160B-6,6S
Min
Max
Min
Max
64
64
ms
128
128
ms
30
40
ns
18
37
20
45
ns
5
10
ns
0
0
ns
8
10
ns
13
25
15
30
ns
0
0
ns
0
7
0
10
ns
8
10
ns
13
15
ns
0
0
ns
0
0
ns
13
15
ns
13
15
ns
1
50
1
50
ns
Note 13: The timing requirements are assumed tT =5ns.
14: VIH(min) and VIL(max) are reference levels for measuring timing of input signals. VIH(min) and VIL(max) of the switching characteristics are
2.0V and 0.8V respectively.
15: tRCD(max) is specified as a reference point only. If tRCD is less than tRCD(max), access time is tRAC. If tRCD is greater than tRCD(max), access
time is controlled exclusively by tCAC or tAA. tRCD(min) is specified as tRCD(min) =tRAH(min) +2tT+tASC(min).
16: tRAD(max) is specified as a reference point only. If tRAD ≥ tRAD(max) and tASC≤ tASC(max), access time is controlled exclusively by tAA.
17: tASC(max) is specified as a reference point only. If tRCD ≥ tRCD(max) and tASC ≥ tASC(max), access time is controlled exclusively by tCAC.
18: Either tDZC or tDZO must be satisfied.
19: Either tCDD or tODD must be satisfied.
20: tT is measured between VIH(min) and VIL(max).
Read and Refresh Cycles
Symbol
Parameter
tRC
Read cycle time
tRAS
RAS low pulse width
tCAS
CAS low pulse width
tCSH CAS hold time after RAS low
tRSH RAS hold time after CAS low
tRCS Read Setup time before CAS low
tRCH Read hold time after CAS high
tRRH Read hold time after RAS high
tRAL
Column address to RAS hold time
tOCH CAS hold time after OE low
tORH RAS hold time after OE low
(Note 21)
(Note 21)
Note 21: Either tRCH or tRRH must be satisfied for a read cycle.
Limits
M5M46X400B-5,5S M5M46X400B-6,6S
M5M46X800B-5,5S M5M46X800B-6,6S ^Unit
M5M465160B-5,5S M5M465160B-6,6S
Min
Max
Min
Max
90
110
ns
50
10000
60
10000 ns
13
10000
15
10000 ns
50
60
ns
13
15
ns
0
0
ns
0
0
ns
10
10
ns
25
30
ns
13
15
ns
13
15
ns
10
MITSUBISHI
Jun. 1999
ELECTRIC