MH8V7245BWZTJ-5 Datasheet, PDF (1/24 Pages) Mitsubishi Electric Semiconductor – HYPER PAGE MODE 603979776 - BIT ( 8388608 - WORD BY 72 - BIT ) DYNAMIC RAM

Preliminary Spec.
Specifications subject to
change without notice.
MITSUBISHI LSIs
MH8V7245BWZTJ -5, -6
HYPER PAGE MODE 603979776 - BIT ( 8388608 - WORD BY 72 - BIT ) DYNAMIC RAM
DESCRIPTION
The MH8V7245BWZTJ is 8388608-word x 72-bit dynamic
ram module. This consist of nine industry standard 8M x 8
dynamic RAMs in TSOP and one industry standard
EEPROM in TSSOP.
The mounting of TSOPs and TSSOP on a card edge dual
in-line package provides any application where high
densities and large of quantities memory are required.
This is a socket-type memory module ,suitable for easy
interchange or addition of module.
FEATURES
Type name
/RAS /CAS Address /OE Cycle Power
access access access access
time time time time time dissipation
(max.ns) (max.ns) (max.ns) (max.ns) (min.ns) (typ.W)
MH8V7245BWZTJ-5 _{50 13 25 13 84 3.51}
MH8V7245BWZTJ-6 _{60 15 30 15 104 2.93}
PIN CONFIGURATION
85pin 1pin
94pin
95pin
10pin
11pin
Utilizes industry standard 8M x 8 RAMs in TSOP and industry
standard EEPROM in TSSOP
168-pin (84-pin dual dual in-line package)
Single +3.3V(±0.3V) supply operation
Low stand-by power dissipation
16.2mW(Max) . . . . . . . . . . . . . . . . . . . LVCMOS input level
Low operation power dissipation
MH8V7245BWZTJ -5 . . . . . . . . . . . . . . . . . . 4.22W(Max)
MH8V7245BWZTJ -6 . . . . . . . . . . . . . . . . . . 3.89W(Max)
All input are directly LVTTL compatible
All output are three-state and directly LVTTL compatible
Includes(0.22uF x 9) decoupling capacitors
4096 refresh cycle every 64ms
Hyper-page mode,Read-modify-write,
/CAS before /RAS refresh,Hidden refresh capabilities
Gold plating contact pads
Row Address A0 ~ A11
Column Address A0 ~ A10
APPLICATION
Main memory unit for computers , Microcomputer memory
BACK SIDE
124pin 40pin
125pin 41pin
FRONT SIDE
168pin 84pin
MIT-DS-0287-0.0
MITSUBISHI
ELECTRIC
( 1 / 24 )
9/Nov./1998