MH8S64BBKD-10 Datasheet, PDF (1/55 Pages) Mitsubishi Electric Semiconductor – 536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM

Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8S64BBKD-10,-10L
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
DESCRIPTION
The MH8S64BBKD is 8388608 - word by 64-bit
Synchronous DRAM module. This consists of eight
industry standard 8Mx8 Synchronous DRAMs in
TSOP and one industory standard EEPROM in
TSSOP.
The mounting of TSOP on a card edge Dual Inline
package provides any application where high
densities and large quantities of memory are
required.
This is a socket type - memory modules, suitable for
easy interchange or addition of modules.
FEATURES
Frequency
-10,-10L 100MHz
CLK Access Time
(Component SDRAM)
8.0ns(CL=3)
Utilizes industry standard 8M x 8 Synchronous DRAMs
TSOP and industry standard EEPROM in TSSOP
144-pin (72-pin dual in-line package)
single 3.3V±0.3V power supply
Clock frequency 100MHz(max.)
Fully synchronous operation referenced to clock rising
edge
4 bank operation controlled by BA0,1(Bank Address)
/CAS latency- 2/3(programmable)
Burst length- 1/2/4/8/Full Page(programmable)
Burst type- sequential / interleave(programmable)
Column access - random
Auto precharge / All bank precharge controlled by A10
Auto refresh and Self refresh
4096 refresh cycle /64ms
LVTTL Interface
APPLICATION
main memory or graphic memory in computer systems
PCB Outline
(Front)
1
(Back)
2
MIT-DS-0244-0.4
MITSUBISHI
ELECTRIC
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15/Jan./1999