MH64S72VJG-5 Datasheet, PDF (1/57 Pages) Mitsubishi Electric Semiconductor – 4,831,838,208-BIT ( 67,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM

Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH64S72VJG-5,-6
4,831,838,208-BIT ( 67,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
DESCRIPTION
The MH64S72VJG is 67108864 - word x 72-bit Sy nchronous
DRAM module. This consist of eighteen industry standard
64M x 4 Sy nchronous DRAMs in TSOP.
The TSOP on a card edge dual in-line package prov ides any
application where high densities and large of quantities memory
are required.
This is a socket-ty pe memory m odule ,suitable f or easy
interchange or addition of module.
FEATURES
Max.
Frequency
-5
133MHz
-6
133MHz
Access Time from CLK
[component level]
5.4ns
(CL = 3,4 at Latch mode)
5.4ns
(CL = 4 at Latch mode)
Utilizes industry standard 64M X 4 Synchronous DRAMs in
TSOP package , industry standard Resistered buffer in TSSOP
package,industry standard PLL in TSSOP package
Single 3.3V +/- 0.3V supply
Max.Clock frequency 133MHz forFully synchronous operation
referenced to clock rising edge
4-bank operation controlled by BA0,BA1(Bank Address)
/CAS latency -2/3(programmable,at buffer mode)
LVTTL Interface
Burst length 1/2/4/8/Full Page(programmable)
Burst type- Sequential and interleave burst (programmable)
Random column access
Burst W rite / Single W rite(programmable)
Auto precharge / All bank precharge controlled by A10
Auto refresh and Self refresh
8192 refresh cycles every 64ms
Discrete IC and module design conform to
PC133 specification. -5 for PC133 CL2
-6 for PC133 CL3
APPLICATION
Main memory or graphic memory in computer systems
85pin 1pin
94pin
95pin
10pin
11pin
124pin 40pin
125pin 41pin
168pin 84pin
MIT-DS-0385-0.1
MITSUBISHI
ELECTRIC
27.Feb.2001 ₁