MH4V6445BXJJ-5 Datasheet, PDF (1/26 Pages) Mitsubishi Electric Semiconductor – HYPER PAGE MODE 268435456-BIT (4194304-WORD BY 64-BIT)DYNAMIC RAM

Preliminary
Some of contents are subject
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MITSUBISHI LSIs
MH4V6445BXJJ-5,-6,-5S,-6S
HYPER PAGE MODE 268435456-BIT (4194304-WORD BY 64-BIT)DYNAMIC RAM
DESCRIPTION
APPLICATION
This is family of 4194304 - word by 64 - bit dynamic RAM
module. This consists of four industry standard 4Mx16 dynamic
RAMs in TSOP and one industry EEPROM in TSSOP.
Main memory unit for computer,Microcomputer
memory,Refresh memory for CRT.
The mounting of TSOP on a card edge dual in line package _{*:Applicable to self refresh version(MH4V645/6445AXJJ-5S,-6S)}
provides any application where high densities and large of
only
quantities memory are required.
This is a socket-type memory module,suitable for easy
interchange of addition of modules.
FEATURES
RAS
access
time
(max.ns)
CAS
access
time
(max.ns)
Address
access
time
(max.ns)
OE
access
time
(max.ns)
Cycle
time
(min.ns)
MH4V6445BXJJ-5,5S 50
13
25
13
84
MH4V6445BXJJ-6,6S 60
15
30
15
104
single 3.3V± 0.3V supply
Low stand-by power dissipation
7.2mW- - - - - - - - - LVCMOS input level
operating power dissipation
MH4V6445BXJJ-5,5S - - - - 2016 mW(max.)
MH4V6445BXJJ-6,6S - - - - 1872 mW(max.)
Self refresh capability*
Self refresh current - - - - 1600 uA(max.)
All input, output LVTTL compatible and low capacitance
Utilizes industry standard 4Mx16 RAMs in TSOP
and industry standard EEPROM in TSSOP.
Includes decoupling capacitor(0.22uFx4)
Hyper page mode , Read-modify-write,
CAS before RAS refresh,Hidden refresh capabilities.
Early-write mode,OE and W to control output buffer
impedance.
ADDRESS
Part No.
Row Add. Col Add. Refresh
MH4V6445BXJJ A0~A11
A0~A9 ^{/RAS only Ref,Normal R/W}
CBR Ref,Hidden Ref
Refresh Cycle
Normal
S-Version
4096/64ms 4096/128ms
MIT-DS-0233-0.0
MITSUBISHI
ELECTRIC
( 1 / 26 )
24/Jul./1998