MH4S64CWZTJ-12 Datasheet, PDF (1/44 Pages) Mitsubishi Electric Semiconductor – 268435456-BIT (4194304-WORD BY 64-BIT)SynchronousDRAM

Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH4S64CWZTJ-12,-15
268435456-BIT (4194304-WORD BY 64-BIT)SynchronousDRAM
DESCRIPTION
The MH4S64CWZTJ is 4194304-word by 64-bit
Synchronous DRAM module. This consists of sixteen
industry standard 2Mx8 Synchronous DRAMs in
TSOP and one industory standard EEPROM in
TSSOP.
The mounting of TSOP on a card edge Dual Inline
package provides any application where high
densities and large quantities of memory are
required.
This is a socket type - memory modules, suitable for
easy interchange or addition of modules.
FEATURES
85pin 1pin
94pin
95pin
10pin
11pin
Frequency CLK Access Time
-12
83MHz
8.5ns
-15
67MHz
9.5ns
Ut-il1izes indus1tr0y0sMtaHndard 2M x 8 Sy8n.5chnronous DRAMs
TS0OP and inzdustry standard EEPRsOM in TSSOP
168-pin (84-pin dual in-line package)
single 3.3V±0.3V power supply
Clock frequency 83MHz/67MHz
Fully synchronous operation referenced to clock rising
edge
Dual bank operation controlled by BA(Bank Address)
/CAS latency- 2/3/4(programmable)
Burst length- 1/4(programmable)
Burst type- sequential / interleave(programmable)
Column access - random
Auto precharge / All bank precharge controlled by A10
Auto refresh and Self refresh
4096 refresh cycle /64ms
LVTTL Interface
APPLICATION
main memory or graphic memory in computer systems
124pin 40pin
125pin 41pin
168pin 84pin
SPD table
Byte No.
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 126 127
MH4S64CWZTJ-12 80 08 04 0C 09 02 40 00 01 C0 85 00 80 00 06 01 05 02 04 01 01 83 06
MH4S64CWZTJ-15 80 08 04 0C 09 02 40 00 01 F0 95 00 80 00 06 01 05 02 04 01 01 66 06
MIT-DS-0053-0.2
MITSUBISHI
ELECTRIC
( 1 / 44 )
Aug.8.1996