MH32V725BST-5 Datasheet, PDF (1/22 Pages) Mitsubishi Electric Semiconductor – HYPER PAGE MODE 2415919104 - BIT ( 33554432 - WORD BY 72 - BIT ) DYNAMIC RAM

Preliminary Spec.
MITSUBISHI LSIs
MH32V725BST -5, -6
HYPER PAGE MODE 2415919104 - BIT ( 33554432 - WORD BY 72 - BIT ) DYNAMIC RAM
DESCRIPTION
The MH32V725BST is 33554432-word x 72-bit dynamic
ram stacked structural module. This consist of thirty-six
industry standard 16M x 4 dynamic RAMs in TSOP and
two industry standard input buffer in TSSOP.
The mounting of TSOP on a card edge dual in-line package
provides any application where high densities and large of
quantities memory are required.
This is a socket-type memory module ,suitable for easy
interchange or addition of module.
FEATURES
Type name
/RAS /CAS Address /OE Cycle Power
access access access access
time time time time time dissipation
(max.ns) (max.ns) (max.ns) (max.ns) (min.ns) (typ.W)
MH32V725BST-5 50 19 30 19 84 12.8
MH32V725BST-6 60 21 35 21 104 11
PIN CONFIGURATION
85pin 1pin
94pin
95pin
10pin
11pin
Utilizes industry standard 16M x 4 RAMs SOJ and industry
standard input buffer in TSSOP
168-pin (84-pin dual dual in-line package)
Single 3.3V(± 0.3V) supply operation
Low stand-by power dissipation . . . . . . . . . . 135.7mW(Max)
Low operation power dissipation
MH32V725BST -5 . . . . . . . . . . . . . . . . . . 14.96W(Max)
MH32V725BST -6 . . . . . . . . . . . . . . . . . . 13.66W(Max)
All input are directly LVTTL compatible
All output are three-state and directry LVTTL compatible
Includes(0.22 uF x 38) decoupling capacitors
4096 refresh cycle every 64ms (CBR Ref)
8192 refresh cycle every 64ms (RAS Only Ref,Normal R/W)
Hyper-page mpde,Read-modify-write,/CAS before /RAS refresh,
Hidden refresh capabilities
JEDEC standard pin configration & Buffered PD pin
Buffered input except /RAS and DQ
Gold plating contact pads
BACK SIDE
124pin 40pin
125pin 41pin
FRONT SIDE
APPLICATION
Main memory unit for computers , Microcomputer memory
PD&ID TABLE
PD1 PD2 PD3 PD4 PD5 PD6 PD7 PD8 ID0 ID1
-5 1 0 0 0 1 0 0 0 0 0
-6 1 0 0 0 1 1 1 0 0 0
1 = NC , 0 = drive to VOL
PD pin . . . buffered. When /PDE is low, PD information can be read
ID pin . . . non-buffered
1
MIT - DS - 0237-0.0
MITSUBISHI
ELECTRIC
168pin 84pin
27/Jul./1998