MH2S64CWXTJ-12 Datasheet, PDF (1/45 Pages) Mitsubishi Electric Semiconductor – 134217728-BIT (2097152-WORD BY 64-BIT)SynchronousDRAM

Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH2S64CWXTJ-12,-15,-1539
134217728-BIT (2097152-WORD BY 64-BIT)SynchronousDRAM
DESCRIPTION
The MH2S64CWXTJ is 2097152-word by 64-bit
Synchronous DRAM module. This consists of eight
industry standard 1Mx16 Synchronous DRAMs in
TSOP and one industory standard EEPROM in
TSSOP.
The mounting of TSOP on a card edge Dual Inline
package provides any application where high
densities and large quantities of memory are
required.
This is a socket type - memory modules, suitable for
easy interchange or addition of modules.
FEATURES
Frequency
CLK Access Time
(Component SDRAM)
-12
83MHz
8ns(CL=3)
85pin 1pin
94pin
95pin
10pin
11pin
-15
67MHz
9.5ns (CL=2)
-1539
67MHz
9ns (CL=3)
Utilizes industry standard 1M x 16 Synchronous DRAMs
TSOP and industry standard EEPROM in TSSOP
168-pin (84-pin dual in-line package)
single 3.3V±0.3V power supply
124pin 40pin
125pin 41pin
Clock frequency 83MHz/67MHz
Fully synchronous operation referenced to clock rising
edge
Dual bank operation controlled by BA(Bank Address)
/CAS latency- 1/2/3(programmable)
Burst length- 1/2/4/8(programmable)
Burst type- sequential / interleave(programmable)
Column access - random
Auto precharge / All bank precharge controlled by A10
168pin 84pin
Auto refresh and Self refresh
4096 refresh cycle /64ms
LVTTL Interface
APPLICATION
main memory or graphic memory in computer systems
SPD table
Byte No.
0 12 3 4 5 6 7 8
9 10 11 12 13 14 15 16 17 18 19 20 126 127
MH2S64CWXTJ-12
MH2S64CWXTJ-15
MH2S64CWXTJ-1539
80 08 04 0C 08 02 40 00 01 C0 80 00 80 00 06 01 05 02 06 01 01 83 06
80 08 04 0C 08 02 40 00 01 F0 95 00 80 00 06 01 05 02 06 01 01 66 06
80 08 04 0C 08 02 40 00 01 F0 90 00 80 00 04 01 05 02 04 01 01 66 04
MIT-DS-0065-0.2
MITSUBISHI
ELECTRIC
Oct.8.1996
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