MH16V7245BATJ-5 Datasheet, PDF (1/23 Pages) Mitsubishi Electric Semiconductor – HYPER PAGE MODE 1207959552 - BIT ( 16777216 - WORD BY 72 - BIT ) DYNAMIC RAM

Preliminary Spec.
MITSUBISHI LSIs
MH16V7245BATJ -5, -6
HYPER PAGE MODE 1207959552 - BIT ( 16777216 - WORD BY 72 - BIT ) DYNAMIC RAM
DESCRIPTION
The MH16V7245BATJ is 16777216-word x 72-bit dynamic
ram module. This consist of eighteen industry standard 16M
x 4 dynamic RAMs in TSOP and three industry standard input
buffer in TSSOP.
The mounting of TSOP on a card edge dual in-line package
provides any application where high densities and large of
quantities memory are required.
This is a socket-type memory module ,suitable for easy
interchange or addition of module.
FEATURES
Type name
/RAS /CAS Address /OE Cycle Power
access access access access
time time time time time dissipation
(max.ns) (max.ns) (max.ns) (max.ns) (min.ns) (typ.W)
MH16V7245BATJ-5 50 18 30 18 84 7.12
MH16V7245BATJ-6 60 20 35 20 104 5.95
PIN CONFIGURATION
85pin 1pin
94pin
95pin
10pin
11pin
Utilizes industry standard 16M x 4 RAMs TSOP and industry
standard input buffer in TSSOP
168-pin (84-pin dual in-line pacege)
Single 3.3V(+/-0.3V) supply operation
Low stand-by power dissipation . . . . . . . . 121mW(Max)
Low operation power dissipation
MH16V7245BATJ -5 . . . . . . . . . . . . . . . . . 8.53W(Max)
MH16V7245BATJ -6 . . . . . . . . . . . . . . . . . 7.88W(Max)
All input,output LVTTL compatible
Includes(0.22uF x 20) decoupling capacitors
4096 refresh cycle every 64ms (A0~A11)
JEDEC standard pin configration & Buffered PD pin
Buffered input except /RAS and DQ
Gold plating contact pads
BACK SIDE
124pin
125pin
40pin
41pin
FRONT SIDE
APPLICATION
Main memory unit for computers , Microcomputer memory
PD&ID TABLE
PD1 PD2 PD3 PD4 PD5 PD6 PD7 PD8 ID0 ID1
-5 1 1 1 1 1 0 0 0 0 0
-6 1 1 1 1 1 1 1 0 0 0
1 = NC , 0 = drive to VOL
PD pin . . . buffered. When /PDE is low, PD information can be read
ID pin . . . non-buffered
MIT-DS-0277-0.0
MITSUBISHI
ELECTRIC
( 1 / 23 )
168pin 84pin
5/Nov./1998