MH16D72AKLB-10 Datasheet, PDF (1/39 Pages) Mitsubishi Electric Semiconductor – 1,207.959,552-BIT (16,777,216-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module

Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH16D72AKLB-10,75
1,207.959,552-BIT (16,777,216-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module
DESCRIPTION
The MH16D72AKLB is 16777216 - word x 72-bit Double
Data Rate(DDR) Sy nchronous DRAM mounted module.
This consists of 9 industry standard 16M x 8 DDR
Sy nchronous DRAMs in TSOP with SSTL_2 interf ace which
achiev es v ery high speed data rate up to 133MHz.
This socket-ty pe memory m odule is suitable f or main
memory in computer systems and easy to interchange or
add modules.
93pin 1pin
FEATURES
Type name
Max.
Frequency
MH16D72AKLB-75
MH16D72AKLB-10
133MHz
100MHz
CLK
Access Time
[component level]
+ 0.75ns
+ 0.8ns
- Utilizes industry standard 16M X 8 DDR Synchronous DRAMs
in TSOP package , industry standard Registered Buffer in
TSSOP package , and industry standard PLL in TSSOP package.
- Vdd=Vddq=2.5v ±0.2V
- Double data rate architecture; two data transf ers per
clock cy c le
- Bidirectional, data strobe (DQS) is transmitted/receiv ed
with data
- Dif f erential clock inputs (CK0 and /CK0)
- data and data mask ref erenced to both edges of DQS
- /CAS latency - 2.0/2.5 (programmable)
- Burst length- 2/4/8 (programmable)
- Auto precharge / All bank precharge controlled by A10
- 4096 ref resh cy c les /64ms
- Auto ref resh and Self ref resh
- Row address A0-11 / Column address A0-9
- SSTL_2 Interf ace
- Module 1bank Conf igration
- Burst Ty pe - sequential/interleav e(programmable)
- Commands entered on each positiv e CLK edge
APPLICATION
Main memory unit for PC, PCserver
144pin 52pin
145pin 53pin
184pin _92pin
MIT-DS-0397-1.1
MITSUBISHI ELECTRIC
24.Nov.2000
1