M66305AP Datasheet, PDF (1/10 Pages) Mitsubishi Electric Semiconductor – TOGGLE LINE BUFFER

MITMSITUSBUISBHISI H〈DI I〈GDIITGAITLAALSASSPS〉 P〉
M6630M56A63P05/AAPF/APFP
TOTGOGGLGE ^{LLEINLEINBEUBFUFEFRFER}
DESCRIPTION
M66305A Toggle Line Buffer has two 5,120-bit line buffer
memories. It takes in serial data that arrives synchronously
with clock pulses and outputs it in serial at a rate of up to 10
Mbits per second synchronously with external clock pulses.
This buffer employs the double buffer system: While data is
being output, data on the next line can be written on the other
line buffer memory.
FEATURES
• 5,120 × 1bit serial input-serial output line buffer memories
• Data transmission at 10 megabits/second maximum
• Two line buffer memories can be alternated by external
toggle signal.
• Memory capacity can be doubled by cascade connection.
• Because of cascade input pin (CAS1), output potential after
completion of output can be set to either H or L.
• Low noise and high fan-out output (IO = ±24mA guaranteed)
• Every input pin has built-in Schmidt trigger circuit.
• Read counter and write counter can be reset independently.
• RESET, T, CNTRST1 and CNTRST2 are equipped with
negative noise reduction circuit.
APPLICATION
Data buffer between industrial or home-use image data pro-
cessing system and peripheral equipment
PIN CONFIGURATION (TOP VIEW)
GND 1
INPUT CLOCK SICLK 2
INPUT DATA SIDATA 3
INPUT CLOCK ENABLE ICE 4
CASCADE INPUT 1 CAS1 5
GND 6
TOGGLE SIGNAL INPUT
T7
CHIP SELECT INPUT CS 8
RESET INPUT RESET 9
GND 10
20 VCC
19 SODATA OUTPUT DATA
18 SOCLK OUTPUT CLOCK
17 OCE OUTPUT CLOCK ENABLE
16 CAS2 CASCADE INPUT 2
15 CNTRST2 READ COUNTER RESET INPUT
14 CNTRST1 WRITE COUNTER RESET INPUT
13 VCC (5V)
12 BF BUFFER FULL OUTPUT
11 INT WRITE REQUEST OUTPUT
Outline 20P4
GND 1
INPUT CLOCK SICLK 2
INPUT DATA SIDATA 3
INPUT CLOCK ENABLE ICE 4
CASCADE INPUT 1 CAS1 5
NC 6
NC 7
GND 8
TOGGLE SIGNAL INPUT
T9
CHIP SELECT INPUT CS 10
RESET INPUT RESET 11
GND 12
24 VCC
23 SODATA OUTPUT DATA
22 SOCLK OUTPUT CLOCK
21 OCE OUTPUT CLOCK ENABLE
20 CAS2 CASCADE INPUT 2
19 NC
18 NC
17 CNTRST2 READ COUNTER RESET INPUT
16 CNTRST1 WRITE COUNTER RESET INPUT
15 VCC (5V)
14 BF BUFFER FULL OUTPUT
13 INT WRITE REQUEST OUTPUT
Outline 24P2W-A
NC: No Connection
BLOCK DIAGRAM
CHIP SELECT
INPUT
CS
RESET INPUT RESET
WRITE COUNTER
RESET INPUT
CNTRST1
READ COUNTER
RESET INPUT
CNTRST2
INPUT DATA SIDATA
CASCADE INPUT 1 CAS1
INPUT CLOCK SICLK
INPUT CLOCK
ENABLE
ICE
TOGGLE SIGNAL
INPUT
T
Matching
detection circuit
Read counter
Write register
Write counter
AD _S-RAM
5120 bits
DI
D0
WR
AD _S-RAM
5120 bits
DI
D0
WR
Data
buffer
Switch
and P.G.
Toggle F/F
INT
OCE
WRITE REQUEST
OUTPUT
OUTPUT CLOCK
ENABLE
SOCLK OUTPUT CLOCK
SODATA OUTPUT DATA
BF
BUFFER FULL
OUTPUT
1