M66287FP Datasheet, PDF (1/21 Pages) Mitsubishi Electric Semiconductor – 262144-word x 8-bit x 3-FIELD MEMORY

MITSUBISHI <DIGITAL ASSP>
M66287FP
262144-word x 8-bit x 3-FIELD MEMORY
DESCRIPTION
The M66287FP is a high-speed field memory with three FIFO (First In First Out) memories of 262144-word x 8-bit
configuration (2M bits) which uses high-performance silicon gate CMOS process technology. One of three FIFO memories
consists of two FIFO memories of 262144-word x 4-bit (1M bits). Five types of operation can be performed through the
following mode settings:
Mode1 : 3-system delay data output by 3-system individual input of 256K-word x 8-bit FIFO
Mode2 : Simultaneous output of 1 to 3-line delay data by 1-system input of 256K-word x 8-bit FIFO
Mode3 : Simultaneous output of 1 to 2-line delay data by 1-system input of 256K-word x 8-bit FIFO
and,1-system delay data output by 1-system input of 256K-word x 8-bit FIFO
Mode4 : 2-system delay data output by 2-system individual input of 256K-word x 12-bit FIFO
Mode5 : Simultaneous output of 1 to 2-line delay data by 1-system input of 256K-word x 12-bit FIFO
The above-mentioned function is most suitable for image data correction across multiple fields. Because three pieces of
2M-bit FIFO are contained in one chip, a low power consumption of a set can be realized.
FEATURES
z Memory configuration The total memory capacity is 6M bits (static memory).
The following two types of memory configurations can be selected.
262144-word x 8-bit x 3-line configuration
z High - speed cycle
z High - speed access
z Output hold
z Supply voltage
262144-word x 12-bit x 2-line configuration
16.6 ns (Min.)
13.0 ns (Max.)
2.0 ns (Min.)
Internal = 1.8 V ± 0.18 V
I/O = 3.3 V ± 0.3 V
z Variable length delay bit
z Five modes can be selected
z Write and read function can be operated completely independently and asynchronously
z Output
3 states
z Package
100pin QFP (100P6Q-A)
APPLICATION
W-CDMA base station, Digital PPC, Digital television, VTR and so on.
MODE DESCRIPTIONS DRAWING
MODE 1
2M-bit x 3 configuration
8-bit bus I/F
MODE 2
8
8
DA<7:0>
WCKA
256K
x
QA<7:0>
RCKA
WRESA
8-bit
FIFO
RRESA
WEA
REA
8
DA<7:0>
WCKA
WRESA
WEA
256K
x
8-bit
FIFO
8
QA<7:0>
RCKA
RRESA
REA
MODE 3
8
DA<7:0>
WCKA
256K
x
WRESA
8-bit
WEA
FIFO
8
QA<7:0>
RCKA
RRESA
REA
3M-bit x 2 configuration
12-bit bus I/F
MODE 4
MODE 5
12
DA<11:0>
WCKA
WRESA
WEA
256K
x
12-bit
FIFO
12
QA<11:0>
RCKA
RRESA
REA
12
DA<11:0>
WCKA
WRESA
WEA
256K
x
12-bit
FIFO
12
QA<11:0>
RCKA
RRESA
REA
8
8
DB<7:0>
WCKB
256K
x
WRESB
WEB
8-bit
FIFO
QB<7:0>
RCKB
RRESB
REB
8
DC<7:0>
WCKC
WRESC
256K
x
8-bit
FIFO
WEC
8
QC<7:0>
RCKC
RRESC
REC
8
256K
x
8-bit
FIFO
8
QB<7:0>
8
256K
x
8-bit
FIFO
8 _QB<7:0>
8 256K
x
8-bit
FIFO
8
QC<7:0>
8
DC<7:0>
WCKC
256K
x
WRESC
WEC
8-bit
FIFO
8
QC<7:0>
RCKC
RRESC
REC
12
DB<11:0>
WCKB
WRESB
WEB
256K
x
12-bit
FIFO
12
QB<11:0>
RCKB
RRESB
REB
12 256K
x
12-bit
FIFO
12
QB<11:0>
The three pieces of 256K- The three pieces of 256K- The two pieces of 256K- The two pieces of 256K- The two pieces of 256K-
word x 8-bit FIFO can be word x 8-bit FIFO are
word x 8-bit FIFO are
word x 12-bit FIFO can be word x 12-bit FIFO are
operated completely
cascade-connected.
cascade-connected and, a operated completely
cascade-connected.
independently.
Write and read operation piece of 256K-word x 8-bit independently.
Write and read operation
of FIFO after the 2nd line FIFO can be operated
of FIFO at the 2nd line is
is controlled by the read completely independently.
controlled by the read
system pin of the 1st line. Write and read operation
system pin of the 1st line.
of FIFO at the 2nd line is
controlled by the read
system pin of the 1st line.
Note: Please refer to “Pin Assignment Table” in “MODE 4 and MODE 5 OPERATION DESCRIPTIONS” for
assignment of external pins, Dx<11:0> and Qx<11:0> when used in 12-bit bus interface.
© 2002 MITSUBISHI ELECTRIC CORPORATION
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