M66281FP Datasheet, PDF (1/13 Pages) Mitsubishi Electric Semiconductor – 5120 x 8-BIT x 2 LINE MEMORY

MITSUBISHI <DIGITAL ASSP>
M66281FP
5120 x 8-BIT x 2 LINE MEMORY
DESCRIPTION
The M66281FP is high speed line memory that uses high
performance silicon gate CMOS process technology and adopts the
FIFO (First In First Out) structure consisting of 5120 words x 8 bits
x 2.
Since memory is available to simultaneously output 1 line delay and
2 line delay data, the M66281FP is optimal for the compensation of
data of multiple lines.
FEATURES
• Memory configuration 5120 words x 8 bits x 2 (dynamic memory)
• High speed cycle
25 ns (Min.)
• High speed access 18 ns (Max.)
• Output hold
3 ns (Min.)
• Reading and writing operations can be completely carried out
independently and asynchronously.
• Variable length delay bit
• Input/output
TTL direct connection allowable
• Output
3 states
• Q00 – Q07
1 line delay
• Q10 – Q17
2 line delay
APPLICATION
• Digital copying machine, laser beam printer, high speed facsimile,
etc.
When write reset input WRESB is set to "L", the write address
counter of memory only for 1 line delay data is initialized.
When read enable input REB is set to "L", the contents of memory
only for 1 line delay data are output to data outputs Q00 to Q07
and the contents of memory only for 2 line delay data are output to
Q10 to Q17 in synchronization with a rising edge of read clock
input RCK to perform reading operation.
When this is the case, the read address counters of memory only
for 1 line delay data and memory only for 2 line delay data are
incremented simultaneously.
In addition, data of Q00 to Q07 is written into memory only for 2
line delay data in synchronization with a rising edge of RCK. When
this is the case, the write address counter of memory only for 2 line
delay data is then incremented.
When REB is set to "H", operation for reading data from memory
only for 1 line delay and from memory only for 2 line delay data is
inhibited and the read address counter of each memory stops.
Outputs Q00 to Q07 and Q10 to Q17 are placed in a high
impedance state. In addition, the write address counter of memory
only for 2 line delay data then stops.
When read reset input RRESB is set to "L", the read address
counters of memory only for 1 line delay data as well as the write
address counter and read address counter of memory only for 2
line delay data are then initialized.
FUNCTION
When write enable input WEB is set to "L", the contents of data
inputs D0 to D7 are written into memory only for 1 line delay data in
synchronization with a rising edge of write clock input WCK to
perform writing operation. When this is the case, the write address
counter of memory only for 1 line delay data is incremented
simultaneously.
When WEB is set to "H", the writing operation is inhibited and the
write address counter of memory only for 1 line delay data stops.
PIN CONFIGURATION (TOP VIEW)
NC 39
RCK 40
RRESB 41
REB 42
GND 43
VCC 44
Q00 45
Q01 46
Q02 47
NC ⁴⁸
M66281FP
Outline 48P6S-A(QFP)
24 NC
23 D5
22 D6
21 D7
20 GND
19 VCC
18 Q17
17 _Q16
16 Q15
15 _NC
NC : No connection
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