M66256FP Datasheet, PDF (1/11 Pages) Mitsubishi Electric Semiconductor – 5120 x 8-BIT LINE MEMORY (FIFO)

MITMSITUSBUISBHISI H〈DI I〈GDIITGAITLAALSASSPS〉 P〉
M662M56662F56PFP
DESCRIPTION
The M66256FP is a high-speed line memory with a FIFO
(First In First Out) structure of 5120-word × 8-bit configuration
which uses high-performance silicon gate CMOS process
technology.
It has separate clock, enable and reset signals for write and
read, and is most suitable as a buffer memory between de-
vices with different data processing throughput.
FEATURES
• Memory configuration ........................................................
............................. 5120 words × 8-bits (dynamic memory)
• High-speed cycle ............................................. 25ns (Min.)
• High-speed access ......................................... 18ns (Max.)
• Output hold ........................................................ 3ns (Min.)
• Fully independent, asynchronous write and read operations
• Variable length delay bit
• Output .................................................................... 3 states
APPLICATION
Digital photocopiers, high-speed facsimile, laser beam print-
ers.
5125012×^08×-B8IT-BLITINLEINMEEMMEOMROYR(FYIF(FOIF) ^O)
PIN CONFIGURATION (TOP VIEW)
Q0 ← 1
Q1 ← 2
DATA OUTPUT
Q2 ← 3
Q3 ← 4
READ ENABLE INPUT RE → 5
READ RESET INPUT RRES→ 6
GND 7
READ CLOCK INPUT RCK → 8
Q4 ← 9
Q5 ← 10
DATA OUTPUT
Q6 ← 11
Q7 ← 12
24 ← D0
23 ← D1
DATA INPUT
22 ← D2
21 ← D3
20 ← WE WRITE ENABLE INPUT
19 ← WRES WRITE RESET INPUT
18 VCC
17 ← WCK WRITE CLOCK INPUT
16 ← D4
15 ← D5
DATA INPUT
14 ← D6
13 ← D7
Outline 24P2U-A
BLOCK DIAGRAM
WRITE
ENABLE INPUT ^{WE 20}
WRITE
RESET INPUTWRES ¹⁹
WRITE
CLOCK INPUT ^{WCK 17}
VCC 18
DATA INPUT
D0 ~ D7
13 14 15 16 21 22 23 24
INPUT BUFFER
DATA OUTPUT
Q0 ~ Q7
1 2 3 4 9 10 11 12
OUTPUT BUFFER
MEMORY ARRAY OF
5120-WORD × 8-BIT
CONFIGURATION
READ
5 RE _{ENABLE INPUT}
READ
6 RRES _{RESET INPUT}
READ
8 RCK _{CLOCK INPUT}
7 GND
1