M66252P Datasheet, PDF (1/11 Pages) Mitsubishi Electric Semiconductor – 1152 x 8-BIT LINE MEMORY FIFO

MITMSITUSBUISBHISI H〈DI I〈GDIITGAITLAALSASSPS〉 P〉
M662M5626P25/2FPP/FP
1151215x28x-B8IT-BLITINLEINMEEMMEOMROYR(FYIF(FOIF) ^O)
DESCRIPTION
The M66252P/FP is a high-speed line memory with a FIFO
(First In First Out) structure of 1152-word × 8-bit configuration
which uses high-performance silicon gate CMOS process
technology.
It has separate clock, enable and reset signals for write and
read and is most suitable as a buffer memory between
devices with different data processing throughput.
FEATURES
• Memory construction ........................................................
............................. 1152words x 8bits (dynamic memory)
• High-speed cycle ............................................ 50ns (min.)
• High-speed access ........................................ 40ns (max.)
• Output hold ....................................................... 5ns (min.)
• Fully independent, asynchronous write and read opera-
tions
• Variable-length delay bit
• Output .................................................................... 3-state
APPLICATION
Digital photocopiers, high-speed facsimiles, laser beam print-
ers.
PIN CONFIGURATION (TOP VIEW)
Q0 1
Data output ^{Q1 2}
Q2 3
Q3 4
Read enable input RE 5
Read reset input RRES 6
GND 7
Read clock input RCK 8
Q4 9
Data output
Q5 10
Q6 11
Q7 12
24 D0
23 D1
22 D2
Data input
21 D3
20 WE Write enable input
19 WRES Write reset input
18 VCC
17 WCK Write clock input
16 D4
15 D5
14 D6
Data input
13 D7
Outline
24P4Y
24P2W-A
BLOCK DIAGRAM
Write
enable input
WE 20
Write
reset input
WRES
19
Write
clock input
WCK 17
Vcc 18
Data input
D0 D1 D2 D3 D4 D5 D6 D7
24 23 22 21 16 15 14 13
Data output
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
1 2 3 4 9 10 11 12
Input buffer
Output buffer
Memory array
(1152 x 8 bits)
5
RE
Read
enable input
6
RRES
Read
reset
input
8
RCK
Read
clock input
7 GND
1