M66221SP Datasheet, PDF (1/11 Pages) Mitsubishi Electric Semiconductor – 256 x 9-BIT MAIL-BOX

MITMSIUTBSUISBHIIS〈HDIIG〈DITIGAILTAALSSAPS〉SP〉
M6622M16S62P21/SFPP/FP
2562×^569-×BI9T-BMITAIML-ABIOL-XBOX
DESCRIPTION
The M66221 is a mail box that incorporates a complete CMOS shared
memory cell of 256 × 9-bit configuration using high-performance silicon
gate CMOS process technology, and is equipped with two access
ports of A and B.
Access ports A and B are equipped with independent addresses CS,
WE and OE control pins and I/O pins to allow independent and
asynchronous read/write operations from/to shared memory
individually. This product also incorporates a port adjustment
arbitration function in address contention from both ports.
FEATURES
• Memory configuration of 256 × 9 bits
• High-speed access, address access time 40ns (typ.)
• Complete asynchronous accessibility from ports A and B
• Completely static operation
• Built-in port arbitration function
• Low power dissipation CMOS design
• 5V single power supply
• Not Ready output pin is provided (open drain output)
• TTL direct-coupled I/O
• 3-state output for I/O pins.
APPLICATION
Inter-MPU data transfer memory, buffer memory for image processing
system.
FUNCTION
The M66221 is a mail box most suitable for inter-MPU data transfer
which is used in a multiport mode. Provision of two pairs of addresses
and data buses in its shared memory cell of 256 × 9 bit configuration
allows independent and asynchronous read/write operations from/to
two access ports of A and B individually.
This allows access to shared memory as simple RAM when viewing
from one MPU. The concurrent accessibility to shared memory from
two MPUs provides remarkable improvement of a multiport mode
processor system in throughput.
The arbitration function incorporated in the chip decides the first-in
port to assign a higher priority to the access from one MPU, even if
two MPUs contend for selection of the same address in shared
memory from ports A and B. A Not Ready signal “L” is output to the
last-in port and invalidates any access from the other MPU.
As a write operation to memory, one of addresses A0 to A7 is specified.
The CS signal is set to “L” to place one of I/O pins in the input mode.
Also, the WE signal is set to “L”. Data at the I/O pin is thus written
into memory.
As a read operation, the WE signal is set to “H”. Both CS signal and
OE signal are set to “L” to place one of I/O pins in the output mode.
One of addresses A0 to A7 is specified. Data at the specified address
is output to the I/O pin.
When the CS signal is set to “H”, the chip enters a non-select state
which inhibits a read and write operation. At this time, the output is
placed in the floating state (high impedance state), thus allowing OR
tie with another chip. When the OE signal is set to “H”, the output
enters the floating state. In the I/O bus mode, setting the OE signal
to “H” at a write time avoids contention of I/O bus data. When the CS
signal is set to Vcc, the output enters the full stand-by state to minimize
supply current (See Tables 1 and 2).
PIN CONFIGURATION (Top view)
CHIP SELECT INPUT CSA→ 1
WRITE ENABLE INPUT WEA→ 2
NOT READY
OUTPUT
Not
Ready
A^←
3
OUTPUT ENABLE INPUT OEA→ 4
NC 5
 A0A^{→ 6}


A1A^→ 7

A PORT


ADDRESS _
INPUT 
A2A^→ 8
A3A^→ 9
A4A^→ 10


A5A^→ 11


A6A^→ 12
 A7A^→ 13
A PORT
DATA I/O
NC 14
 I/O0A↔ 15


I/O1A↔
16


I/O2A^↔
17
 _I/O3A↔ ₁₈

 I/O4A^↔ 19


I/O5A^↔
20


I/O6A↔
21
 I/O7A↔ 22


I/O8A^↔
23
GND 24
48 VCC
47 ← CSB CHIP SELECT INPUT
46 ← WEB WRITE ENABLE INPUT
45
→ _{Not Ready B}
NOT READY
OUTPUT
44 ← OEB OUTPUT ENABLE INPUT
43 NC
42 ← A0B _
41 ^← A1B


40 ^← A2B


39 ^← A3B  ^{B PORT}
38 ← A4B
 ADDRESS
 INPUT
37 ^← A5B


36 ← A6B ^
35 ^← A7B


34 NC
33 ^↔ I/O8B 
32
↔

I/O7B _
31
↔
I/O6B


30
29
28
↔
↔
↔
I/O5B


I/O4B 
I/O3B


B PORT
DATA I/O
27
↔
I/O2B


26 ^↔ I/O1B 
25
↔

I/O0B _
Outline 48P4B
CHIP SELECT INPUT CSA→ 1
WRITE ENABLE INPUT WEA→ 2
NOT READY
OUTPUT
Not
Ready
A^←
3
OUTPUT ENABLE INPUT OEA→ 4
NC 5
NC 6
 A0A^→ 7


A1A^→ 8


A2A^→ 9
A PORT _
ADDRESS _
INPUT 
A3A^→ 10
A4A^→ 11


A5A^→ 12


A6A^→ 13
 A7A→ 14
NC 15
NC 16
A PORT
DATA I/O
 I/O0A↔ 17


I/O1A↔
18


I/O2A^↔
19


I/O3A↔
20
 I/O4A↔ 21


I/O5A^↔
22


I/O6A↔
23
 _I/O7A↔ 24


I/O8A^↔
25
GND 26
52 VCC
51 ← CSB CHIP SELECT INPUT
50 ← WEB WRITE ENABLE INPUT
49
→ _{Not Ready B}
NOT READY
OUTPUT
48 ← OEB OUTPUT ENABLE INPUT
47 NC
46 NC
45 ^← A0B 
44 ← A1B


43 ← A2B


42 ← A3B  ^{B PORT}
41 ^← A4B
 ADDRESS
 INPUT
40 ← A5B


39 ^← A6B


38 ← A7B 
37 NC
36 NC
35 ^↔ I/O8B 
34
↔

I/O7B _
33
↔
I/O6B


32
31
30
↔
↔
↔
I/O5B


I/O4B 

I/O3B _
B PORT
DATA I/O
29
↔
I/O2B


28 ↔ I/O1B ^
27
↔

I/O0B 
Outline 52P2G-A _{NC: No Connection}
1