M66220SP Datasheet, PDF (1/11 Pages) Mitsubishi Electric Semiconductor – 256 x 8-BIT MAIL-BOX

MITMSIUTBSUISBHIIS〈HDIIG〈DITIGAILTAALSSAPS〉SP〉
M6622M06S62P20/SFPP/FP
2562×^568-×BI8T-BMITAIML-ABIOL-XBOX
DESCRIPTION
The M66220 is a mail box that incorporates a complete CMOS shared
memory cell of 256 × 8-bit configuration using high-performance silicon
gate CMOS process technology, and is equipped with two access
ports of A and B.
Access ports A and B are equipped with independent addresses CS,
WE and OE control pins and I/O pins to allow independent and
asynchronous read/write operations from/to shared memory
individually. This product also incorporates a port adjustment
arbitration function in address contention from both ports.
FEATURES
• Memory configuration of 256 × 8 bits
• High-speed access, address access time 40ns (typ.)
• Complete asynchronous accessibility from ports A and B
• Completely static operation
• Built-in port arbitration function
• Low power dissipation CMOS design
• 5V single power supply
• Not Ready output pin is provided (open drain output)
• TTL direct-coupled I/O
• 3-state output for I/O pins
APPLICATION
Inter-MPU data transfer memory, buffer memory for image processing
system.
PIN CONFIGURATION (Top view)
CHIP SELECT
INPUT
CSA^→ 1
WRITE ENABLE
INPUT
WEA ^→
2
NOT READY
OUTPUT
Not
Ready
A
←
3
OUTPUT
INPUT
ENABLE
OEA
→
4
 A0A→ 5

 A1A→ 6

 A2A→ 7

A PORT  A3A→ 8
ADDRESS 
INPUT  A4A^→ 9

 A5A^→ 10


A6A^→ 11


A7A→ 12
A PORT
DATA I/O
 I/O0A↔ 13

 I/O1A↔ 14

 I/O2A↔ 15

 I/O3A^↔ 16

 I/O4A^↔ 17

 I/O5A^↔ 18

 I/O6A^{↔ 19}


I/O7A
↔
20
GND 21
42 VCC
41 ← CSB
CHIP SELECT
INPUT
40
← _WEB
WRITE
INPUT
ENABLE
39
→ Not
Ready B
NOT READY
OUTPUT
38 ^← OEB
OUTPUT ENABLE
INPUT
37 ← A0B 

36 ← A1B 

35 ← A2B 

34 ← A3B  B PORT
 ADDRESS
33 ^← A4B  INPUT

32 ^← A5B 
31 ← A6B


30 ← A7B


29 ↔ I/O7B 

28 ↔ I/O6B 

27 ↔ I/O5B 

26
25
↔
↔
I/O4B
I/O3B



B PORT
DATA I/O

24 ↔ I/O2B 

23 ↔ I/O1B 

22 ↔ I/O0B 
Outline
42P4B
42P2R-A
BLOCK DIAGRAM
NOT READY
OUTPUT Not Ready A 3
WRITE
ENABLE
INPUT
WEA
2
CHIP
SELECT INPUT
CSA
1
OUTPUT
ENABLE INPUT
OEA
4
I/O0A 13
I/O1A 14
I/O2A 15
A PORT DATA I/O
I/O3A 16
I/O4A 17
I/O5A 18
I/O6A 19
I/O7A 20
A PORT
ADDRESS INPUT
A0A 5
A1A 6
A2A 7
A3A 8
A4A 9
A5A 10
A6A 11
A7A 12
VCC
42
CONTROL
CIRCUIT
ARBITRATION
CIRCUIT
CONTROL
CIRCUIT
A0A
OEA WEA
A7A
8
I/O BUFFER
A0B
WEB OEB
A7B
8
I/O BUFFER
8 _ROW/COLUMN
DECODER
MEMORY ARRAY OF
256-WORD × 8-BIT
CONFIGURATION
ROW/COLUMN ⁸
DECODER
21
GND
NOT READY
39 Not Ready B ^OUTPUT
40 WEB
WRITE
ENABLE INPUT
41 CSB
CHIP
SELECT INPUT
38 OEB
OUTPUT
ENABLE INPUT
22 I/O0B
23 I/O1B
24 I/O2B
25 I/O3B
26 I/O4B
B PORT DATA I/O
27 I/O5B
28 I/O6B
29 I/O7B
37 A0B
36 A1B
35 A2B
34 A3B
33 A4B
32 A5B
31 A6B
30 A7B
B PORT
ADDRESS INPUT
1