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M66006P Datasheet, PDF (1/5 Pages) Mitsubishi Electric Semiconductor – 12-BIT I/O EXPANDER
MITMSITUSBUISBHISI H〈DI I〈GDIITGAITLAALSASSPS〉 P〉
M660M0666P00/6FPP/FP
DESCRIPTION
The M66006 is a semiconductor integrated circuit which has
12-bit shift register function to execute serial-parallel conver-
sion and parallel-serial conversion.
Because a serial-parallel shift register and a parallel-serial
shift register are independently built in this IC, it is possible to
read serial input data to a shift register while converting par-
allel data into serial data. Also, parallel data I/O pins can be
set to input mode or output mode bit-by-bit.
The M66006 can be widely used for I/O port expansion of
MCU, serial bus system data communication, etc.
FEATURES
• Bi-directional serial data communication with MCU
• Read of serial data during parallel-serial conversion.
• Bit resolution of serial data I/O
• Low power dissipation (50µW/package max.)
(VCC=5V, Ta=25°C, in quiescing)
• Schmitt input (DI, CLK, S, CS)
• Open drain output (DO, from D1 to D12)
• Parallel data I/O (from D1 to D12)
• Wide operating supply voltage range (VCC=2 to 6V)
• Wide operating temperature range (Ta =–20 to 75°C)
APPLICATION
Serial-parallel data conversion, parallel-serial data conver-
sion, serial bus control by MCU.
BLOCK DIAGRAM
12-1B2IT-BII/TOI/EOXEPAXNPADNEDRER
PIN CONFIGURATION (TOP VIEW)
Serial data output DO ← 1
Serial data input DI → 2
Clock input CLK → 3
Chip select input CS → 4
VCC 5
Set input S → 6
GND 7
Parallel data
outputs
DD1121
↔
↔
8
9
GND 10
DO D1
DI
D2
CLK D3
CS D4
D5
S
D6
D7
D12 D8
D11 D9
D10
20
19
18
17
16
15
14
13
12
11
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10

Parallel
data
I/O
Outline 20P4
20P2N-A
Clock input CLK 3
Set input S 6
Chip
select input CS 4
Serial
data input DI 2
VCC
5
Shift register !
DO
D12 D11 D10
D3 D2 D1
Q12 Q11 Q10
Q3 Q2 Q1
Parallel output latch
D12 D11 D10
D3 D2 D1
Q12 D11 D10
Q3 Q2 Q1
Shift register @
D1
7
10
GND GND
Serial
1 DOdata output
20 D1 


19 D2




18 D3















11
D10




9
D11



8
D12


VCC
CLK
S
CS
DI
Input form
VCC
DO
Output form
VCC
D1~D12
1