M65667FP Datasheet, PDF (1/9 Pages) Mitsubishi Electric Semiconductor – PICTURE-IN-PICTURE SIGNAL PROCESSING

PRELIMINARY
Notice:This is not a final specification.
Some parametric limits are subject to change.
MITSUBISHI ICs (TV)
M65667FP
PICTURE-IN-PICTURE SIGNAL PROCESSING
DESCRIPTION
The M65667FP is a NTSC PIP (Picture in Picture) signal
processing LSI, whose sub and main-picture inputs are composite
and Y/C separated signals, respectively. The built-in field memory
(96k-bit RAM) ,V-chip data slicer and analog circuitries lead the PIP
system low cost and small size.
FEATURES
• Built-in 96k-bit field memory (sub-picture data storage)
• Internal V-chip data slicer (for sub-picture)
• Vertical filter for sub-picture (Y signal )
• Single sub-picture (selectable picture size : 1/9 , 1/16)
• Sub-picture processing sepecification (1/9 size / 1/16 size) :
Quantization bits
Y, B-Y, R-Y : 6bits
Horizontal sampling 171 pixels (Y) , 28.5 pixels (B-Y, R-Y)
Vertical lines
69/ 52 lines
• Frame (sub-picture) on/off
• Built-in analog circuits :
Two 8-bit A/D converters (main and sub-picture signals)
Two 8-bit D/A converters (Y and C sub-picture signals)
Sync-tip-clump, VCXO, Analog switch ... etc.
• I²C BUS control (parallel/serial control) :
PIP on/off , Sub-picture size(1/9 or 1/16), Frame on/off
(programmable luma level), PIP position (4 corners fixed
position), Picture freeze , Y delay adjustment, Chroma level, Tint,
Black level, Contrast ... etc.
APPLICATION
NTSC color TV
RECOMMENDED OPERATING CONDITION
Supply voltage range........................................................3.1 to 3.5V
Operating frequency.........................................................14.32 MHz
Operating temperature....................................................-20 to 75°C
Input voltage (CMOS interface) "H"........................VDD×0.7 to VDD V
"L".............................0 to VDD×0.3V
Output current (output buffer)........................................±4mA (MAX)
Output load capacitance............................................20pF (MAX) ^∗1
Circuit current.........................................................................160mA
NOTICE: Connect a 0.1µF or larger capacitor between VDD and VSS
pins.
∗1 : Include pin capacitance (7pF)
PIN CONFIGURATION (TOP VIEW)
NC 49
TEST8 50
Y-PIP 51
TEST9 52
Yin 53
TESTEN 54
Cin 55
AVss (ana) 56
AVss3 (VCXO) 57
VCXO out 58
VCXO in 59
FILTER 60
BIAS 61
AVdd3 (VCXO) 62
AVdd2 (m) 63
AVdd2 (m) 64
M65667FP
Outline 64P6N-A
32 NC
31 VD/CSYNC/TEST6
30 HD/TEST5
29 SWM/TEST4
28 MCK
27 fsc/TEST3
26 BGP (m)/TEST2
25 DVdd2 (ram)
24 DVss2 (ram)
23 CLK
22 DATA
21 ACK
20 CSYNC (s)/TEST1
19 SCK
18 BGP (s)/TEST0
17 NC
NC : NO CONNECTION
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